/Learning the Behaviour of Future HPC Systems: Predictive Modelling and Hardware–Software Co-Design

Learning the Behaviour of Future HPC Systems: Predictive Modelling and Hardware–Software Co-Design

PhD - Leuven | Just now

Enabling predictive understanding and intelligent optimization of HPC applications across next-generation computing architectures.

High-Performance Computing (HPC) is undergoing a fundamental transformation. Future systems will increasingly combine heterogeneous processors, accelerators, advanced memory hierarchies, and high-speed interconnects, while scientific applications are evolving toward complex ML+HPC hybrid workloads that combine numerical simulation, machine learning, data analytics, and AI-driven scientific discovery. This growing diversity makes it increasingly difficult to predict how current and future applications will perform on hardware architectures that have not yet been built or extensively evaluated.

 

Traditional performance models typically rely on analytical assumptions or measurements from existing systems. Machine-learning approaches offer an opportunity to learn complex relationships directly from application executions and hardware behaviour. However, a key challenge remains: a model trained on existing architectures may not generalize reliably to future architectures, particularly when both hardware characteristics and software implementations evolve.

 

This PhD research aims to develop a data-driven and physics-grounded framework for learning the interaction between applications and computing architectures. The central idea is to learn not only application runtime, but the underlying execution behaviour that determines performance such as compute utilization, memory behaviour, parallelism, communication, and architectural bottlenecks. Application execution data will provide empirical knowledge of real systems, while simulation and physics-based information will provide a means of grounding and constraining predictions beyond the range of currently available hardware.

 

The research will investigate how such learned models can generalize across hardware generations and potentially across different architectural paradigms, while accounting for changes in application implementations. Ultimately, the goal is to develop predictive models capable of estimating the performance and behaviour of emerging HPC workloads on future architectures, and to use these models to support hardware/software co-design and architectural exploration.

 

The research will contribute toward a new generation of performance modelling in which empirical data, machine learning, and physics-based knowledge are combined to predict and explain application behaviour beyond currently observed computing systems.


 


 

Required background: Computer Science, Electrical(electronics) Engineering

Type of work: 40% simulation/modeling 40% data analysis 20% literature

Supervisor: Roel Wuyts (KU Leuven)

Co-supervisor: Roel Wuyts (KU Leuven)

Daily advisor: Udari De Alwis

The reference code for this position is 2027-130. Mention this reference code in your application.

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