Machine Learning for Hybrid Memory Arbitration

IMEC's STCO program is designed to pioneer future technology scaling, overcoming challenges such as the scaling wall, memory wall, power wall, and cost wall. Our mission is to engineer high-density, cost-effective Integrated Circuits (ICs), optimizing Power, Performance, Area, Cost, and Temperature (PPACT). By fostering innovation as Artificial Intelligent (AI) methodologies and adopting a system-level perspective, we confront these challenges head-on. 

We are seeking a motivated intern with a keen interest in system-level design and optimization. The successful candidate will participate in the design and implementation of an Hybrid Memory Controller (HMC) based on Machine Learning (ML). Responsibilities include design and optimize RTL code and implement it on a FPGA, also defining benchmarks for debugging and evaluate the memory performance.  

The intern will also engage in dynamic tasks like defining different benchmarks for debugging, evaluating the memory performance and propose improvements for ensuring low power consumption. 

Required background: background in Electronics/Computer engineering, RTL coding (HDL/systemVerilog), logical FPGA synthesis, basic understanding of DDR protocols, programming (C++/bash). 

 
Type of work: This role is designed to enrich your learning experience, providing a blend of theoretical knowledge and practical application. The work is divided into 25% literature study to enhance theoretical comprehension and 75% hands-on implementation design.