In-Memory processing architecture for sensor fusion on edge

Autonomous systems require hardware architectures and technologies which should simultaneously have high performance and low power to support intelligence deployment at the edge and by extracting/fusing information from several sensors. Today, computer engines are based mainly on the Von-Neumann architecture, which faces significant limitations such as power wall, memory wall and ILP (Instruction Level Parallelism) wall, making them unsuitable for low-power Intelligent systems. Not to mention that they are typically implemented using the traditional volatile CMOS technology, which also suffers from increasing static power, reducing reliability, and increasing cost as the device technology further scales down. Therefore, there is a need not only for alternative computing architectures in the light of new device (non-volatile) technologies but also for new algorithms to process sensory data on the new computing paradigm efficiently.

This project aims to develop and design energy efficient computer architectures using non-volatile devices inspired by the brain features like low-precision, sparse and distributed parallel processing, followed by exploring neuromorphic sensory fusion algorithms with online learning/adaptivity for energy-efficient computing and algorithms for hardware efficiency and co-optimization. This topic builds on extensive prior experience within the neuromorphic team of imec.