/In-Memory processing architecture for sensor fusion on edge

In-Memory processing architecture for sensor fusion on edge

PhD - Leuven | More than two weeks ago

Algorithm-hardware co-optimization, making use of computation-in-memory concepts and inspired by the brain to address challenges in edge processing of event-based sensor fusion applications.

Autonomous systems require hardware architectures and technologies which should simultaneously have high performance and low power to support intelligence deployment at the edge and by extracting/fusing information from several sensors. Today, computer engines are based mainly on the Von-Neumann architecture, which faces significant limitations such as power wall, memory wall and ILP (Instruction Level Parallelism) wall, making them unsuitable for low-power Intelligent systems. Not to mention that they are typically implemented using the traditional volatile CMOS technology, which also suffers from increasing static power, reducing reliability, and increasing cost as the device technology further scales down. Therefore, there is a need not only for alternative computing architectures in the light of new device (non-volatile) technologies but also for new algorithms to process sensory data on the new computing paradigm efficiently.

This project aims to develop and design energy efficient computer architectures using non-volatile devices inspired by the brain features like low-precision, sparse and distributed parallel processing, followed by exploring neuromorphic sensory fusion algorithms with online learning/adaptivity for energy-efficient computing and algorithms for hardware efficiency and co-optimization. This topic builds on extensive prior experience within the neuromorphic team of imec.



Required background: Electrical engineering with Analog design experience

Type of work: 45% hardware implementation, 45% algorithm implementation, 10% benchmarking

Supervisor: Said Hamdoui

Daily advisor: Amirreza Yousefzadeh, Matthias Hartmann

The reference code for this position is 2024-081. Mention this reference code on your application form.

Who we are
Accept marketing-cookies to view this content.
Cookie settings
imec's cleanroom
Accept marketing-cookies to view this content.
Cookie settings

Related jobs

Development of power gating circuitry model

Develop an electrical equivalent model for power gating circuitry, including the chip power pads, power gating switches, active circuitry, PDN etc., aiming to facilitate the evaluation of trade-offs of novel technology assumptions across the stack. 

Accuracy Comparison of Liberty timing models (NLDM vs. ECSM vs. CCS vs. CCSN) beyond FinFET nodes

Dive deep into the world of VLSI implementation technologies and the methodologies used to develop them 

Staff and Operations Manager

Within Specialty Components and Platforms Development (SCPD) unit, we are looking for a motivated and enthusiastic colleague to lead staff and operational activities. Currently this position is mapped at manager level with the outlook of growing further in the organization.

Senior R&D Engineer: Electronic System Architecture

We are looking for an enthusiastic person eager to take ownership during the whole electronic system design and development cycle.

Layout and tape-out engineer DST/SCPD

As tape-out and lay-out engineer, you will play a key role to support IC manufacturing in advanced technologies for logic scaling, Si Photonics, Imagers, Life Science, GaN Power and other specialties.

Real-time monitoring of the remaining useful life of an electronic system with a data-based approach

The aim of this PhD track is to develop an AI methodology, using machine learning (ML) approaches, to predict the remaining useful lifetime of electronic systems by fusing data obtained from both sensors and simulations.
Job opportunities

Send this job to your email