Morphological investigation of Josephson junctions for superconducting technologies

Superconducting computing technologies based on Josephson junctions (JJs) offer a promising route toward ultra‑fast and energy‑efficient processors, far surpassing the limits of conventional CMOS transistor‑based CPUs. However, state‑of‑the‑art Nb‑based JJs face critical scalability barriers, including limited critical current density (Jc < 1 mA/µm²), relatively large device dimensions (>250 nm), low kinetic inductance, and a restricted thermal budget (~200 °C) that hinders integration with CMOS‑compatible processes.

To overcome these limitations, recent developments have demonstrated NbTiN/α‑Si/NbTiN Josephson junctions fabricated using a semi-damascene process on 300 mm wafers, achieving Jc ≈ 2–3 mA/µm² and critical dimensions down to 210 nm, enabling denser and lower‑loss superconducting circuits.

A key challenge for further technology scaling is understanding and controlling electrical variability arising from the tunnel barrier, where barrier thickness fluctuations, roughness, and local composition variations directly affect junction resistance, and device reproducibility.

The goal of this bachelor project is to investigate how deposition parameters impact the morphology of the α‑Si‑based JJ barrier. By analyzing TEM and EDS cross‑sectional images from differently processed samples, we aim for:

1. Quantify barrier thickness, interface roughness, and material uniformity.
2. Identify correlations between process conditions and morphological variations.
3. Develop a phenomenological model that predicts electrical variability as a function of deposition parameters.

This project provides hands‑on experience with advanced nanoscale characterization techniques, materials analysis, and structure–property relationships in superconducting devices contributing to the continued scaling of high‑performance JJ‑based computing technologies.