[NanoIC topic] Electrical Test Structure Design for Advanced Interconnects

As advanced interconnect patterning approaches sub-20 nm dimensions, conventional evaluation methods based on yield, defects, and line resistance become increasingly insufficient to capture the true impact of process variations on circuit performance. While recent High-NA Direct Metal Etch (DME) demonstrations have achieved functional structures with excellent electrical yield, the relationship between lithographic metrics such as critical dimension variation, line edge roughness, and pattern transfer quality and their resulting impact on electrical performance remains largely unexplored. [Master int...rs for DME | PowerPoint]

This internship aims to bridge that gap by developing and evaluating electrical test structure concepts capable of translating nanoscale process variations into circuit-relevant metrics. The work will focus on the design, modeling, and simulation of candidate structures, such as delay monitors, RC test vehicles, and oscillator-based approaches, using representative interconnect geometries and process variation inputs. Through circuit-level simulations, the student will assess the sensitivity of different test concepts to expected manufacturing variations and define practical measurement requirements for future implementation. [Master int...rs for DME | PowerPoint]

The outcome will be a set of design recommendations and simulation-based guidelines that enable a transition from simple pass/fail process qualification toward quantitative performance assessment of advanced interconnect technologies. This work will provide a foundation for future electrical characterization vehicles and contribute to a deeper understanding of how patterning innovations translate into system-level benefits.