Reliability of next generation DRAM memories

Background:  

• Current trends like artificial intelligence and autonomous cars call for DRAM chips to be ever faster and have larger capacity.
• Imec enables the continuous evolution of DRAM by pathfinding architectures and materials for future DRAM chips.
• To be adopted, any new development has to guarantee performance during planned lifetime, ie, be reliable.
• In this master thesis/internship, the reliability of devices with different gate dielectrics materials and gate metals will be evaluated by different accelerated testing.
• Your main objective is to define adequate accelerated testing procedures to extrapolate lifetime.
• The results obtained by the different accelerated testing methods will be compared in view of the physics of degradation and their ability for confident projections.

Expected work:

• Measurements and analysis (60-70%):
  • Electrically measure leakage and gate oxide breakdown of devices and find methodology to account for competing degradation mechanisms.
  • Analyze the statistics and physics of gate oxide breakdown.
  • Model the different physics happening during gate oxide breakdown.
  • Scripting in python for analysis and modeling.
• Reporting (30-40%):
  • Reporting data to colleagues.
  • Report/thesis writing.

Type of Project:  Combination of internship and thesis; Internship; Thesis

Master's degree: Master of Science; Master of Engineering Science

Master program: Electrotechnics/Electrical Engineering; Materials Engineering; Physics; Nanoscience & Nanotechnology; Chemistry/Chemical Engineering

Duration: 4 months to 1 year

For more information or application, please contact the supervising scientist Joao Bastos (joao.bastos@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.