Silicon-Calibrated Interconnect Reliability & Aging Digital Twins with Sensor-Embedded Test Chips for Workload-Aware Systems

Background and Motivation

As semiconductor technologies continue to scale, reliability challenges increasingly arise from the complex interaction between device aging, interconnect degradation, and workload-dependent operating conditions. Current reliability assessment methodologies remain largely device-centric and fail to adequately propagate aging and degradation effects across the design hierarchy, from devices and interconnects to circuits, architectures, and system-level functionality.

Furthermore, coupled degradation mechanisms in both BEOL and FEOL structures, including electromigration (EM), stress migration (SM), thermomechanical effects (TM), and transistor aging, can lead to significant performance drifts such as timing shifts, frequency degradation, power inflation, and ultimately reduced system lifetime. Existing reliability flows typically lack a closed-loop framework that links silicon measurements with predictive system-level reliability models. In addition, given the increasing AI chip power densities, the coupling between reliability and thermal aspects is crucial.

Research Objective

The objective of this PhD is to develop a cross-layer, silicon-calibrated reliability digital twin framework that enables predictive lifetime assessment and real-time reliability management of advanced semiconductor systems.

The proposed framework will:

• Propagate degradation effects from interconnect levels to circuits, architectures, and system functionality.
• Capture workload- and mission-profile-dependent aging behavior.
• Model the coupled electro-thermal-mechanical degradation of BEOL structures considering latest interconnect technology options.
• Integrate embedded sensor measurements for continuous model calibration and validation.
• Enable predictive reliability assessment and adaptive aging mitigation strategies at runtime.

Research Methodology

The project will combine physics-based reliability modeling, machine learning, and silicon validation through dedicated reliability test vehicles.

Key activities include:

1. Cross-Layer Reliability Modeling
• Develop models linking BEOL and 3D interconnect degradation mechanisms to circuit and system-level performance metrics.
• Quantify the propagation of aging-induced parametric shifts across abstraction levels.

2. Machine Learning-Based Digital Twin Development
• Create fast surrogate models capable of predicting reliability evolution under realistic workloads.
• Fuse physics-based models with data-driven approaches to improve prediction accuracy and scalability.

3. Sensor-Embedded Reliability Test Chips
• Design and fabricate dedicated ASIC/FPGA-based reliability demonstrators containing embedded monitors and on-chip sensors.
• Utilize silicon measurements for parameter extraction, calibration, and model closure.

4. Runtime Reliability Management
• Develop adaptive mitigation techniques including workload allocation, thermal management, and reliability-aware throttling.
• Demonstrate real-time digital twin operation for predictive health monitoring.

Expected Impact

The proposed research will establish a novel reliability-aware digital twin methodology connecting silicon measurements to predictive system-level reliability assessment. The resulting framework will enable:

• More accurate lifetime prediction of advanced integrated systems.
• Reduced design margins through silicon-calibrated reliability models.
• Early detection of aging-induced performance degradation.
• Reliability-aware operation of future high-performance and AI computing platforms.
• Strengthened European leadership in trustworthy semiconductor technologies and digital-twin-based system engineering.

Type of Work:

70% physics-based modelling and machine learning, 30% experimental characterization.

Required Background:

MSc in Engineering sciences, Engineering technology, Physics or computer Science.

Supervisory team: Daily Advisor: Ahmed Saleh (imec), Promotor: Prof. Dr. Ir. Houman Zahedmanesh (imec+KU Leuven)

Relevant reading:

[1] H. Zahedmanesh, “Electromigration in Nano-Interconnects: Determining Reliability Margins in Redundant Mesh Networks Using a Scalable Physical-Statistical Hybrid Paradigm,” Micromachines, vol. 15, no. 8, p. 956, 2024.

[2] A. S. Saleh, K. Croes, H. Ceric, I. De Wolf, and H. Zahedmanesh, “A Comprehensive Microstructure-Aware Electromigration Modeling Framework: Investigation of the Impact of Trench Dimensions in Damascene Copper Interconnects,” Nanomaterials, 2024.

[3] A. S. Saleh, K. Croes, H. Ceric, I. De Wolf, and H. Zahedmanesh, “AI-Driven Variability-Aware Physics-Based EM Simulation Framework for jmax Estimation,” in Proc. IEEE Int. Interconnect Technology Conf. (IITC), 2025.

[4] S. Esposto, I. Ciofi, G. Sisto, K. Croes, D. Milojevic, and H. Zahedmanesh, “Unit-Cell-Based Approach for Electromigration Compliance Checks in VLSI Power Delivery Networks,” IEEE Trans. Device Mater. Rel., 2025.

[5] Esposto, S.; Farr, H.; Grate, L.; Chavez, T.; Thesberg, M.; Schneider, H.; Ciofi, I.; Sisto, G.; Croes, K.; Milojevic, D.; Zahedmanesh, H.,“IR-drop-based Electromigration-Compliance Checks of Grid Unit-Cells in Power Delivery Networks,” Proceedings of the IEEE International Interconnect Technology Conference (IITC), 2026.

[6] H. Zahedmanesh, P. Roussel, I. Ciofi, and K. Croes, “A Pragmatic Network-Aware Paradigm for System-Level Electromigration Predictions at Scale,” in Proc. IEEE Int. Reliability Physics Symp. (IRPS), 2023.

[7] H. Zahedmanesh, I. Ciofi, O. Zografos, M. Badaroglu, and K. Croes, “A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network,” in Proc. 23rd ACM/IEEE Int. Workshop on System-Level Interconnect Pathfinding (SLIP), 2021, pp. 1–7, doi: 10.1109/SLIP52707.2021.00008.