Sub-THz Packaging solution for High-Bandwidth Wireline applications in Datacenter, HPC, and Optical Platforms

1. Motivation and Background
The explosive growth of AI training, inference, HPC workloads, and cloud-scale systems has pushed electrical I/O architectures to their limits. As data rates exceed 100–200 Gb/s per lane, traditional pluggable optical modules struggle with power, loss, and bandwidth-density constraints. Co-Packaged Optics (CPO) integrates optical transceivers directly on the package/interposer, drastically shortening electrical paths and enabling lower power, higher bandwidth interconnects. This shift demands advanced RF/mixed-signal interposers /packaging capable of ultra-low-loss routing, embedded passives, and tight EIC–PIC integration.

2. Problem Statement
Future systems require multi-Tb/s throughput, low-loss RF paths, high-density wireline channels, and sub-pJ/bit energy efficiency. Current interposer/packaging platforms suffer from parasitics, crosstalk, limited Q-factor in embedded passives, and steep insertion loss beyond 70 GHz. A unified electrical–photonic–packaging co-design approach is essential to achieve next-generation performance targets.

3. Research Objectives

• Develop low-loss, high-density routing for ASIC–Driver–PIC links in imec RF interposer/Mix signal interposer/packaging
• Design high-Q inductors, capacitors, and matching networks.
• Explore hybrid integration combining on-chip active components with interposer-embedded passives.
• Design and simulate high-speed SerDes channels with low jitter and high energy efficiency.

4. Methodology

• Modeling & Simulation: EM modeling, SerDes and system-level SI/PI analysis.
• RF Interposer/packaging Design: Optimization of routing, RDL stack, shielding, and via transitions. Embedded passives designed for maximum Q-factor.
• Hybrid Co-Design: Combined EIC–PIC–interposer simulation to optimize jitter, bandwidth, IL/RL, and pJ/bit.
• Experimental Validation: S-parameter measurements, eye diagrams, and full benchmarking.

Expected Outcomes

• High-speed, low-power SerDes demonstrator tailored for wireline application
• RF/mixed-signal interposer design with minimized parasitics and crosstalk.
• High-Q embedded passives reducing ASIC area and cost.

Master's degree: Master of Engineering Science, Master of Science

Required educational background: Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics

University promotor: Nadine Collaert (VUB)

For more information or application, please contact the supervising scientist Xiao Sun (xiao.sun@imec.be).