Thermalization Physics in Quantum Devices: Implications for Large-Scale Quantum Systems

Thermalization Physics in Quantum Devices: Implications for Large-Scale Quantum Systems

In recent years, advances in engineering and control of individual quantum systems have led to the development of small, noisy intermediate-scale quantum processors (NISQ) with infidelities below the quantum-error correction threshold. However, the path to large-scale, error-corrected quantum processors is still a long way ahead. Among the many experimental implementations considered today, solid-state qubits, namely superconducting and spin qubits, have emerged as popular candidates due to their compatibility with CMOS fabrication techniques, offering potential scalability and integration into existing semiconductor technologies, including the upcoming technology areas namely cryo-CMOS electronics and/or single flux quantum (SFQ) devices.

Building error-corrected quantum processors necessitates densely connected qubits, readout, and control elements. Traditionally, superconducting and spin qubits are arranged in a 2D array on-chip, but this poses a wiring bottleneck for further scaling. Transitioning to 3D-integration using superconducting flip-chip tech and through-substrate vias (TSVs) addresses this challenge by stacking qubits and control elements in separate chips. This approach boosts qubit density, addressability, and interconnect efficiency. It also allows seamless integration of qubits with peripheral devices like quantum noise-limited amplifiers, cryo-electronics etc.

However, the above envisioned system architecture introduces new challenges related to thermal management at cryogenic temperatures, primarily due to poor electron-phonon coupling of materials used in these chips. The current understanding of cryogenic modelling for CMOS circuits also remains limited, primarily due to the absence of comprehensive transistor models at these extremely low temperatures. Passive heat loads of wiring components and on-chip power dissipation coupled with the limited cooling power of commercial dilution refrigerators presents thermal design constraints for large-scale systems. This necessitates accurate thermal modelling to optimize performance and reliability, effectively addressing issues associated with heat dissipation, inter-chip thermal resistance, thermal gradients, thermal crosstalk, and potential on-chip hotspots. As the chips undergo thermal cycling during device cooldowns and operational cycles, aging-related concerns arise, further emphasizing the critical role of thermal modelling in ensuring the long-term reliability and operational stability of qubits.

What you will do:

• Explore/generate thermal models to study: inter-chip thermal resistance, thermal gradients, thermal crosstalk in quantum devices.
• Investigate the fundamental heat transport at very low temperatures and find accurate simplifications how to translate this in a usable model.
• Feedback on models from measurements of quantum devices with cryo-CMOS electronics.

Who you are: 

• You have a Master’s degree in electrical engineering, microelectronics, applied physics, computational physics, or related fields.
• You would like to explore new challenges in engineering large scale-quantum processors
• You are self-motivated, like to take initiatives, and a team-player.
• Given the international character of imec, a fluent knowledge of English is necessary.