Machine learning is transforming our world by increasingly influencing different aspects of our life. Some of the most powerful machine learning algorithms, called deep learning algorithms or deep neural networks, demonstrate state-of-the-art performance on a range of tasks. Although impressive, this high performance comes at a cost: Deep learning algorithms require billions of computations during inference, and require high power and performance, as well as large memories to store the weights of the trained networks. This makes them hard to use in mobile and IoT devices at the edge.
To enable energy efficient inference, a wide variety of accelerators is being created, both in research (eg MIT Eyeriss, KULeuven Envision) and in industry (eg Google TPU, IBM, Tesla,…). In the same vein, also NVIDIA has created and open sourced a dedicated inference accelerator: The NVIDIA Deep Learning Accelerator (see nvdla.org) is an open and modular architecture that promotes a standard way to design deep learning inference accelerators, allowing support for a wide range of applications and energy constrained devices.
This project will study the nvdla architecture and will instantiate it for a few typical IoT applications, e.g. keyword spotting in audio, object detection in images or videos. The work will consist in creating and training the neural networks, sizing and configuring an accelerator for it and mapping the network on the instantiated accelerator. Power, performance and accuracy trade-offs will be studied in a foundry CMOS technology as well as on an FPGA demo board.
Type of project: Thesis, Combination of internship and thesis
Duration: 10 months
Required degree: Master of Engineering Science
Required background: Electrotechnics/Electrical Engineering
Only for self-supporting students