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ADC (Analog Digital Converter) 11 ENOB 170MS/s

This 170 MS/s 11 ENOB 1.36 mW pipelined SAR ADC with complementary residue amplifier in 40 nm CMOS is a good candidate for the latest wireless standards.

Macro Name  ADC (Analog Digital Converter) 11 ENOB 170MS/s
Short Description(max 128 characters)  This 170 MS/s 11 ENOB 1.36 mW pipelined SAR ADC with complementary residue amplifier in 40 nm CMOS is a good candidate for the latest wireless standards.
Extra description (optional) Imec offers a white-box IP license with support on a 170 MS/s 11 ENOB 1.36 mW pipelined SAR (Successive Approximation Register) ADC with complementary residue amplifier in 40 nm digital CMOS. Each ADC channel of the 2x interleaved ADC consists of a 6 bit coarse SAR, a dynamic residue amplifier, a 8 bit fine SAR. The complementary dynamic single-stage residue amplifier reuses charge that is typically wasted during the reset phase, and hence improves efficiency by a factor 2 in this block. This ADC achieves a SNDR of 67 dB from 20 to 1710 MS/s at 10 MHz input frequency. The energy is about 4.2 fJ per conversion step at 10 MHz up till 170 MHz clock frequency, and 9 fJ per copnversion step at Nyquist frequency at 170 MHz clock frequency.
This low power ADC is a good data converter candidate for the latest wireless standards.
Market category Communications - Data processing - Consumer Electronics
Possible applications & standards This ADC is a good candidate for next generation Software Defined Radio ( SDR ) receivers, including LTE Advanced and the emerging generation of WIFI IEEE 802.11ac.
Primary Category  Analog & Mixed Signal IP:A2D Converter
Node / process 40nm Low Power CMOS
Foundry  TSMC
Maturity  Silicon proven on prototypes, hence only white-box license (no corner characterization performed for high volume production)
Leaflet or datasheet URL  
Conference where this IP has been published ESSCIRC 2014
Paper publication URL Download the paper publication here
Chip area(for Hard IP only) (um**2) 68400
Width (for Hard IP only) (um) 380 um
Height (for Hard IP only) (um) 180 um
Power (uW/MHz) 8 uW/MHz
Constant Power (mW) 1.360 mW @ 170 MS/s
Constant Leakage Power (uW) < 10 uW (at 1.1V)
  • 180um by 380um ADC in 40nm digital CMOS
  • 170 MS/s
  • 11 ENOB (effective number of bits)
  • low noise peak SNDR of 67 dB at 20 MS/s and 10 MHz input, SNDR of 59.8 dB at 170 MS/s and 85 MHz
  • pipelined SAR (Successive Approximation Register)
  • complentary dynamic single stage residue amplifier
  • low power of 1.36 mW at 1.1 V
  • SFDR (spurious free dynamic range) is 68 dB for 136 Mz sampled at 260 MS/s
  • energy 4 fJ/conversion step at 20MS/s and 10MHz frequency ; 9 fJ/conversion step at 170 MS/s and Nyquist frequency
  • Schreier FOM (Figure-of-Merit) is 177.78 dB at 20 MS/s
  • whitebox IP license with technology transfer training and support
  • evaluation boards with ADC samples
  • Option 3