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ADC (Analog Digital Converter) 11bit 410MS/s

This 410 MS/s 11 bit 2.1 mW dynamic pipelined SAR ADC with on-chip background calibration in 28nm CMOS is suited for LTE-Advanced wireless receivers.

Macro Name  ADC (Analog Digital Converter) 11bit 410MS/s
Short Description(max 128 characters)  410 MS/s 11 bit 2.1 mW dynamic pipelined SAR ADC with on-chip background calibration in 28nm CMOS - suited e.g. for LTE-Advanced wireless receivers.
Extra description (optional) Imec offers a white-box IP license with support on a 410 MS/s 11 bit 2.1 mW dynamic pipelined SAR (Successive Approximation Register) ADC with background calibration in 28nm digital CMOS. Each ADC channel of the 2x interleaved ADC consists of a 6 bit coarse SAR, a dynamic residue amplifier, a 7 bit fine SAR, and an on-chip calibration engine. The latter detects and corrects comparator offsetsand amplifier gain errors in the background. This ADC achieves a SNDR of 59.8 dB at 410 MS/s for an energy of 6.5 fJ per conversion step. 
This ADC is a good candidate for LTE-Advanced wireless receivers, and its results have been published at VLSI Circuits Symposium of 2013.
Market category Communications - Data processing - Consumer Electronics
Possible applications & standards This ADC is a good candidate for next generation Software Defined Radio ( SDR ) receivers, including LTE Advanced and the emerging generation of WIFI IEEE 802.11ac.
Primary Category  Analog & Mixed Signal IP:A2D Converter
Node / process 28 nm digital HPM CMOS
Foundry  TSMC
Maturity  Silicon proven on prototypes, hence white-box license (no corner characterization performed for high volume production)
Leaflet or datasheet URL  
Conference where this IP has been published VLSI Circuits Symposium 2013
Paper publication URL Download the publication here
Chip area(for Hard IP only) (um**2) 108500
Width (for Hard IP only) (um) 310 um - including the calibration engine, excluding the decoupling capacitance
Height (for Hard IP only) (um) 350 um
Power (uW/MHz) 5 uW/MHz for ADC + 3.3 uW/MHz for calibration
Constant Power (mW) 5 uW/MHz for ADC + 3.3 uW/MHz for calibration
Constant Leakage Power (uW) 90 uW
  • ADC in 28nm digital CMOS
  • 410 MS/s
  • 11 bit
  • low noise peak SNDR of 62.5 dB at 10 MS/s, SNDR of 59.8 dB at 410 MS/s, combined with a low power of 2.1 mW at 0.9V supply
  • dynamically pipelined SAR (Successive Approximation Register)
  • dynamic residue amplifier
  • on-chip calibration engine (with programmable clock rate to trade-off power consumption versus background calibration convergence speed)
  • SFDR (spurious free dynamic range)is 68 dB for 136 Mz sampled at 260 MS/s
  • energy of 3.7 fJ per conversion step at 40 MS/s and low input frequency ; energy of 12.8 fJ per conversion step at 410 MS/s and at the Nyquist frequency
  • 0.11 mm**2 including on-chip calibration engine
  • whitebox IP license with technology transfer training and support
  • evaluation boards with ADC samples
  • Option 3