This article was originally published in Semiconductor Digest – July/August 2025 issue
The semiconductor industry is expanding at an unprecedented pace. The global chip market, valued at $627.6 billion in 2024, is expected to reach over $1 trillion by 2030, driven by demand from data centers, wireless communications, and automotive applications. At the same time, AI infrastructure growth is amplifying this trend, as the chips powering AI models contribute significantly to embodied emissions—accounting for 30% of the total carbon footprint in AI-driven data centers. This rapid expansion adds to existing environmental concerns.
Semiconductor manufacturing is among the most resource-intensive industries, requiring vast amounts of energy, water, and chemicals. The production of integrated circuits (ICs) alone accounts for 185 million tons of CO₂ equivalent emissions annually, making it a major contributor to global carbon footprints. The use of various chemicals in semiconductor manufacturing contributes to greenhouse gas emissions and long-term environmental contamination. Additionally, the industry relies on large-scale water consumption for wafer fabrication and produces hazardous chemical waste, further straining environmental resources. As the demand for advanced chips grows, addressing these sustainability challenges becomes paramount to mitigate the sector’s role in the broader climate challenge.
In this article, we will analyze various simulated sustainability scenarios and demonstrate real-fab examples of environmental impact reduction covering lithography, etch, and wet processes. The simulations were performed with imec.netzero’s framework that can identify the processes with the highest carbon footprint, pinpoint inefficiencies, and propose targeted improvements. By combining modelling insights with real-world data, we highlight actionable strategies that can drive reductions in emissions, water use, and resource consumption across semiconductor manufacturing.
Imec.netzero
The simulations in this article were carried out using imec.netzero. This web application framework offers a quantitative approach to identifying environmental impact hot spots by assessing multiple factors—energy consumption, water use, and chemical emissions—across various semiconductor technologies. Using a virtual fab representative of a generic high volume manufacturing entity, imec.netzero models the effects of different strategies, such as transitioning to green energy, improving water recirculation, or optimizing process efficiency, across these interconnected factors. Unlike other models, it provides actionable data down to the process level, allowing projections for future technologies and identification of high-impact processes that contribute the most. This data-driven approach allows engineers to focus on the most effective levers for change.
A key aspect of imec.netzero is its ability to analyze emissions at multiple levels within the fab environment. Corporate reporting has driven emission assessments down to the facility level. For semiconductor fabs, it is relevant to have granular data both where wafer processing occurs and at the subfab level, where utilities such as chillers, emission abatement, and equipment power are controlled. This dual-layer approach enables targeted improvements in both wafer processing and facility operations.
The examples presented here will illustrate how imec.netzero can guide the semiconductor industry in reducing emissions, optimizing resource consumption, and minimizing chemical use—demonstrating a data-driven approach to sustainability without compromising technological progress. Note that all results are indicative of a virtual high-volume manufacturing fab and depend on the assumptions made for quantities like yield, volumes, tool utilization, die size and other factors.
Figure 1 - The imec.netzero framework provides a comprehensive life cycle analysis of IC manufacturing, assessing multiple impact factors such as energy consumption, water use, and chemical emissions. The dual-layer view covers both wafer processing and facility operations, offering actionable data to identify high-impact processes and propose effective sustainability strategies.
Categorizing emissions in scopes
The semiconductor industry contributes significantly to greenhouse gas emissions, driven by its high energy consumption and extensive use of process gases and materials. These emissions stem from direct process emissions, electricity consumption, and the supply chain. To systematically assess them, the Greenhouse Gas (GHG) Protocol classifies emissions into three scopes: Scope 1 (direct emissions from process gases), Scope 2 (indirect emissions from electricity use), and Scope 3 (upstream emissions from materials and equipment). Quantifying emissions in CO₂ equivalents provides a unified metric for comparing the environmental impact of different semiconductor processes and ensures that all major emission sources are accounted for when developing sustainability strategies.
Addressing lithography’s Scope 2 emissions impact
As semiconductor technologies advance, the energy required to manufacture each wafer continues to rise. Comparing the impact of N28 and N2 logic nodes reveals that an advanced N2 logic node generates approximately 1,600 kg CO₂eq per wafer (depending on the user-selected variables including how the electricity is generated), with dry etch and lithography alone contributing nearly 40% of total emissions. Process-level modeling further shows that lithography’s electricity consumption increases with each technology node, driven by the high energy demands of advanced exposure tools and the growing complexity of patterning steps required. As a result, Scope 2 emissions from electricity consumption can make up 60% of the total carbon footprint, highlighting the need for energy-efficient process innovations and low-carbon energy sources.
Figure 2 – (Left) Comparison of emissions between N28 and N2 logic nodes, highlighting the significant contribution of Scope 2 emissions from electricity consumption that increases for more advanced logic nodes. This example is for industry average electrical grid mix and 100% abatement. (Right) The breakdown of the N2 technology’s total emissions by process reveals that dry etch and lithography alone contributing nearly 40% of total emissions.
One effective strategy for reducing patterning emissions is the transition to Extreme Ultraviolet (EUV) lithography, which eliminates many of the multi-patterning steps required in deep ultraviolet (DUV) lithography. For example, an analysis of N7 logic node fabrication shows that moving from a 193i-based process to an EUV-based one significantly lowers energy consumption per wafer, reducing overall emissions. However, despite these benefits, lithography remains one of the most energy-intensive steps in semiconductor manufacturing, necessitating further optimization.
Another key area of focus is dose reduction—minimizing the energy required to expose photoresist while maintaining critical imaging performance. Lowering the dose increases tool throughput (wafers per hour), thereby reducing the total energy consumption per wafer. Imec continuously optimizes resist materials and process conditions to enable, to give a recent example, an 18% dose reduction for a 28 nm pitch pattern (indicative of imec’s N5 logic node). This effort not only reduces Scope 2 emissions but also lowers overall resource consumption.
Beyond emissions
While the Scope 1-3 framework provides a structured way to categorize emissions, it does not always paint a complete picture of the environmental impact of individual process optimizations. It is important to avoid shifting the impact while optimizing for one factor. Considering lithography, as a specific example, lowering environmental impact is not just about reducing the Scope 2 emissions generated because of the electricity consumed, it also involves factors like material circularity and resource depletion. Incorporating material use and water consumption alongside emissions therefore makes it possible to evaluate different strategies side by side, particularly for complex steps like lithography where energy use, chemical selection, and throughput are all interdependent.
A comprehensive spider chart view to capture environmental impact
Complementary to the emission scopes, imec introduces a spider chart view to offer a complete assessment of environmental impact and a way to compare impact over different processes or techniques. It currently aggregates five environmental impact categories (Scope 1, Scope 2, Scope 3, material scarcity (Abiotic Depletion Potential (ADP)), and water use) into a single comparative chart. In the future, additional inventory items such as PFAS (per- and polyfluoroalkyl substances) could be integrated into the same methodology, providing a more comprehensive assessment of chemical-related environmental risks.
For example, in the case of lithography dose reduction, the 18% lower dose does not just reduce Scope 2 emissions from electricity use—it also decreases material consumption and lowers direct emissions from process gases. The spider chart captures this combined effect, revealing an 11% total environmental impact reduction.
Figure 3 - The plot shows that despite an 18% lower EUV dose, line width roughness remains comparable across four different resists, indicating no significant trade-off in imaging quality. The spider chart quantifies the benefits of using a lower EUV dose, showing an 11% total environmental impact reduction.
Tackling Scope 1 emissions in dry etch
As the semiconductor industry gradually transitions to greener energy sources, such as solar, wind, and low-carbon electricity grids, emissions from electricity consumption (Scope 2) decrease. However, this shift makes direct process emissions from gases (Scope 1) the dominant contributor to semiconductor manufacturing’s carbon footprint. For an N2 logic node, dry etch emerges as the largest source of Scope 1 emissions, primarily due to the use of high-GWP (Global Warming Potential) gases like CF4 and NF3. While abatement can reduce these emissions by a factor of 10, CF4 remains a major challenge due to its low Destruction and Removal Efficiency (DRE) during abatement.
There are three general strategies to reduce dry etch emissions:
- Improving abatement – A straightforward solution, but it still leaves residual emissions and introduces its own energy and material footprint.
- Optimizing process recipes – A more complex but effective approach that reduces gas use at the source.
- Switching to alternative low-GWP gases – A long-term solution requiring significant development but with high potential impact.
As an example of recipe optimization, imec developed Transient Assisted Processing (TAP), a novel etch technique that reduces process gas consumption. Unlike conventional Reactive Ion Etching (RIE), where gases flow continuously, TAP introduces extremely short, controlled gas pulses, allowing residual gas in the chamber to be used more efficiently. When applied to a hard mask open process, TAP eliminated two of three high-GWP gases entirely and reduced CF4 consumption by 98% compared to the original process, significantly lowering Scope 1 emissions. However, the initial environmental assessment revealed unintended trade-offs: while Scope 1 emissions dropped, the longer process time increased Scope 2 energy consumption and material use, leading to a higher overall environmental impact. A hybrid approach, combining TAP with RIE for the thickest layer, restored the overall throughput while maintaining the lower process consumption of the high GWP gases.
This case highlights the importance of holistic sustainability metrics. While Scope 1-3 frameworks pinpoint emission sources, a balanced view ensures that optimizations truly lead to lower overall environmental impact rather than shifting the burden elsewhere.
Figure 4 – The new hybrid TAP process combines steps from RIE and TAP, eliminating two high-GWP gases and reducing CF4 consumption. The chart reflects the lower overall environmental impact, compared to the RIE reference and the original TAP approach.
Countering Scope 3 emissions by reducing material consumption
With the industry’s transition to low-carbon energy and implementation of effective abatement, Scope 3 emissions will represent a larger share of the total footprint. The semiconductor industry relies on a wide range of critical materials, including silicon, copper, and rare earth elements, all of which face increasing demand from both the electronics sector and green technologies (think about wind turbines, solar photovoltaics, and electric vehicles). This competition for materials puts added pressure on the supply chain and also contributes to Scope 3 emissions through the energy-intensive processes involved in extracting, transporting, and processing these materials.
Furthermore, semiconductor fabrication itself consumes large volumes of chemicals and ultrapure water (UPW), adding to Scope 3 emissions. Simulations for an N2 logic node indicate that wet processing dominates material consumption, accounting for ~50% of total chemical use per wafer and a major share of UPW consumption. Given this, reducing material use in wet processes presents a major opportunity for lowering Scope 3 impact.
The backside wafer cleaning process, for example, provides an opportunity for improving material efficiency. Traditionally known as SCROD (Single-wafer spin Cleaning with Repetitive use of Ozonated water and Diluted HF), this method has been in use for over 30 years and relies on a cyclical oxidation-etching process. While effective, this process is resource-intensive, requiring high chemical and ultrapure water (UPW) consumption.
To address this, imec developed the HydroFluoric Ozonated Mixture (FOM) clean, a more efficient, single-step and self-limiting process, controlled by time, temperature, and chemical concentration. Testing showed that FOM clean achieved similar performance to the SCROD process in terms of silicon loss, particle removal, and surface roughness. However, it delivered major sustainability advantages by significantly reducing resource consumption including a twofold reduction in water use and increased throughput due to its faster processing time.
FOM’s reduced environmental footprint is driven by improvements in multiple impact categories, including Scope 3 emissions (from lower chemical and water use), Scope 2 emissions (from reduced energy consumption), and ADP (due to less natural resource consumption).
Figure 5 – FOM is more than two times faster than SCROD, without impact on process performance. Moreover, it uses two times less water, reflected in a 37% lower environmental impact.
Embracing a circular economy: reuse and recycle
Beyond reducing absolute material use, improving circularity —such as recycling chemicals or reusing ultrapure water— can further drive sustainability and decrease dependence on the market. The semiconductor supply chain involves various stages, from raw materials used in equipment and subcomponents to those consumed in fabs, outsourced assembly, and final products. Each of these stages offers concrete opportunities to improve material circularity. Practices like onsite recovery and reuse, offsite material recovery, and recycling packaging materials can significantly reduce waste, conserve valuable resources, and help mitigate supply chain pressures on raw materials.
Improving material circularity in semiconductor manufacturing can ease the growing demand for finite resources (copper, cobalt, and rare earth elements), ultimately reducing Scope 3 emissions. By recycling and reusing critical materials within the supply chain, the industry can reduce its reliance on raw material extraction and processing, addressing both resource scarcity and emissions.
It is essential to consider process changes at the fab or process level in tandem with strategies for maintaining high yield. Even small reductions in yield can lead to substantial increases in emissions. For instance, in an N2 advanced logic node, a 2% yield loss for a large die results in approximately 42 tons of CO₂ equivalent emissions—three times the total per capita emissions in the US in 2023. Given that a sustainable per capita target is around 2 tons of CO₂ equivalent per year, optimizing yield is crucial to minimizing environmental impact. Maintaining high yield while implementing sustainable practices ensures that emission reductions are meaningful and not inadvertently offset by increased resource consumption.
Figure 6 - Yield for a 10mm x 10mm die size and the full field yield. The yield is a critical factor in semiconductor manufacturing, as it directly impacts the number of functional chips produced from a wafer. Higher yields indicate more efficient production processes and lower environmental impact per chip.
Opportunities and barriers of sustainability in the semiconductor industry
The semiconductor industry can significantly reduce its environmental impact by focusing on several key strategies. First, identifying efficiencies at the process level and transitioning to low-carbon energy sources is crucial. Second, climate-aware process development, alongside opportunities to reduce, reuse, and recycle materials, can further drive sustainability across the supply chain.
However, barriers exist—cost of change is a significant challenge. To overcome this, introducing lower-environmental impact processes early in development and budgeting for new approaches is necessary. Another challenge is the need for increased awareness of the environmental impact of various processes, which can be addressed by deploying tools to quantify and communicate environmental performance across the organization.
In addition to environmental benefits, these sustainability efforts bring significant advantages to the semiconductor industry. For example, improving material efficiency and reducing energy consumption can lead to lower operational costs. This includes potential savings through faster processing times, fewer raw material dependencies, and more effective use of existing resources. Optimizing resource use also reduces waste and improves yield, which can translate directly into cost savings.
Want to know more?
- For a deeper dive into this topic, check out the keynote presentation by Emily Gallagher (imec) titled "Transformation: Climate-Aware IC Manufacturing" at the recent 2025 SPIE Advanced lithography + Patterning conference, Paper 13424-6.
- You can find more details about EUV dose reduction in this research paper: Mihir Gupta, et al. “EUV dose reduction for pitch 28 nm line-space” SPIE Photomask Technology + EUV Lithography, 2024.
- Stay tuned for more information about the hybrid TAP approach in the upcoming paper: A Fathzadeh, P Bezard, et al. – Transient –Assisted Processing: the path to sustainable patterning - Manuscript in preparation
- Complementary to this article, you can find more information on imec’s efforts to reduce PFAS in photoresists and other lithographic processes in the 2025 SPIE Advanced lithography + Patterning conference, paper 13428-37.
