26 February - 02 March 2023 | San Jose, California, United States
The event for emerging technology in the semiconductor industry
This year at SPIE Advanced Lithography + Patterning, imec has a record number of 70 contributions, of which 42 first authored papers and 28 co-authored papers. These papers show imec’s progress in advanced patterning challenges, such as (High NA) EUV lithography, CFET patterning, DRAM patterning, and the supporting role of machine learning techniques. Next to that, imec is leveraging nanoimprint lithography for bioelectronic applications, and will be giving an invited talk about its progress.
With sustainability becoming an increasingly more important aspect for chip design and manufacturing, imec has initiated a project that looks into sustainable semiconductor manufacturing techniques for lithography and etch. Imec will introduce several solutions for reduction, recycling and recovery of various materials used in high-impact areas of these manufacturing techniques. Emily Gallagher, a principal member of the technical staff, will also be a panelist at the SPIE AL+P with a panel on “Sustainability and Lithography’s Role”.
Finally, imec will host one course on stochastic lithography, given by John S. Petersen, scientific director of Advanced Patterning.
Having put complementary FET (CFET) on the logic technology roadmap, imec is now looking into the patterning challenges faced by the next generations of transistor architectures. The following selection of papers report progress on sequential and monolithic CFET patterning processes:
Read more about CFET in imec’s stories
Imec is preparing the High NA patterning ecosystem for the imec-ASML Joint High NA Lab, which will be centered around the first 0.55NA extreme ultraviolet (EUV) lithography prototype tool and will be key to advance Moore’s Law beyond 2nm technology generations. Progress is reported in developing patterning and etch processes, in screening new resist and underlayer materials, in improving metrology and photomask technologies, as presented in the following selection of papers:
Imec leverages its partners in the semiconductor industry, material companies and fundamental research to develop innovative EUV pellicle design, used to protect the photomask from contamination during high-volume semiconductor manufacturing. After earlier announcing the first successful fabrication and scanner handling of full-field CNT-based pellicles, imec presents recent optimizations and results in following papers:
As part of its Sustainable Semiconductor Technologies and Systems program, imec is looking into sustainable semiconductor manufacturing techniques for lithography and etch. Using a virtual lab at process level, imec identifies the highest impact areas to reduce the impact of both lithography and etch emissions associated with fabricating an N2 logic wafer.
View all imec contributions here.
Attend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose
Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications.