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Sustainable semiconductor technologies and systems (SSTS)

Throughout the semiconductor ecosystem, there’s a will to make more sustainable choices. Imec offers support, starting with the inclusion of environmental metrics in technology pathfinding.

For decades, striking the ideal balance between low power, high performance, small area and minimal cost (PPAC) was the main concern for manufacturers of integrated circuits (ICs). But the worldwide fight against ecological degradation and climate change compels them to include their environmental impact into the equation – making PPAC-E the new formula for sustainable progress.

Of course, digital technologies can play an important role in reducing global emissions, but there’s no denying the ecological footprint of the IC industry in terms of:

  • extraction and refinement of (sometimes scarce) raw materials
  • use of water, electricity and gases (some with high global warming potential) during manufacturing
  • e-waste
ICs

ICs often contain rare and valuable materials. But because of the high level of integration, these are difficult to recycle.

Reducing that footprint is not only a matter of corporate responsibility, but also of compliance to local and global regulations and – in the case of reliance on critical materials – long-term business continuity.

Join our SSTS program

Need for a detailed picture of environmental impact of IC production

The first and crucial step towards downsizing the environmental footprint of the IC manufacturing process is finding a way to quantify that footprint and its constituting elements.

At the moment, the industry lacks such a holistic approach. It gets only glimpses of the full picture from information published by equipment and material suppliers, and from IC foundries that measure the environmental impact after the production. What it needs is a way to correctly assess the impact of future IC technologies – when there’s still time to adjust the PPAC-E balance.

In its first phase, it’s this quantification that imec’s SSTS program aims to achieve.

Framework to predict impact

Why is imec in an ideal position to lead this effort? For one thing, we have access to all the necessary information. A result of our strong ties to all the players in the industry and the experience in our own cleanrooms.

Secondly, imec uses an established framework for design-technology co-optimization (DTCO) that can be expanded to include environmental parameters. At the moment, our software tool is able to estimate energy consumption, water usage and greenhouse gas emissions for present and future logic CMOS technologies. That information makes it possible to take sustainability into account when making technology choices, for instance by compensating the increased use of electricity with more renewable energy use, or steering research in the direction of processes with lower emission levels.

Read this article for a detailed overview of our framework and its findings.

We will extend this to:

  • other parameters such as use of raw materials and chemicals
  • other technologies such as DRAM and Flash
  • other system levels such as packaging and PCBs

Targeted improvements

Ultimately, imec’s SSTS program can raise awareness on the environmental impact of IC production throughout the ecosystem, and enlighten the path towards targeted improvements. These can range from the increased use of renewable energy or recycling to the implementation of alternative materials and fabrication processes.

Want to know more? Are you interested in joining this program so you can help shape its roadmap and get privileged access to research results?

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