3D NAND DTCO

This project will establish a DTCO workflow for 3D NAND like “string” memories, focusing on how array architecture, periphery partitioning, and die to die bonding jointly determine PPAT (power performance area thermal). At array level, we will model string stacking, staircase routing, WL/BL RC, vertical coupling, and sensing margins using an evaluation framework already outlined for high density “3D string memory inspired by 3D NAND architecture,” adapting it from internal XTCO memory activities.

For periphery, we will define what stays local versus what is offloaded to a bonded die (drivers, decoders, sense amps, redundancy/repair), and quantify IR drop and timing impacts under realistic array + periphery floorplans, following the DTCO macro level recommendations discussed with partners (array/periphery co design, bank sizing, and interconnect parasitics).   On bonding, we will parameterize hybrid bond pitch scaling—including parasitic R/C of die to die links at sub micron pitch—and propagate those into array level read/write latency and energy models; recent internal analyses show bonding resistance and capacitance trends and how they impact 3D memory performance at fine pitches.   
 

Type of Internship: Thesis; Internship; Master internship; Combination of internship and thesis

Master's degree: Master of Engineering Science; Master of Science

Required educational background: Electrotechnics/Electrical Engineering

Duration: >4 months

For more information or application, please contact the supervising scientists Arvind Sharma (Arvind.Sharma@imec.be), Aakash Patel (aakash.patel@imec.be) and Bowen Wang (Bowen.Wang@imec.be).