3D SRAM Memory Design in Nanofabric

Project type: Master Thesis / Internship, with the option of pursuing a Ph.D. afterward.

Duration: 6-9 months, consisting of 2 months at IMEC (Leuven, Belgium), and the remaining time at LIRMM (Montpellier, France)

Summary: Design of a 3D SRAM memory macro in a disruptive 3D process technology

Description:

In recent years, novel fabrication approaches like parallel and monolithic 3D integration have emerged to meet the demand for cost-effective integrated circuits. These methods involve stacking devices, wafers, or dies to reduce the footprint, latency, and power consumption compared to traditional 2D designs. However, parallel 3D has limitations in vertical connections, and monolithic 3D is constrained by high costs. 

This student project investigates an emerging monolithic 3D integration approach called 3D Nanofabric, which was recently proposed by IMEC. 3D Nanofabric offers the prospect of future cost-effective circuit integration by concurrently processing multiple identical vertically stacked tiers. The student will design and implement a 3D static random-access memory (SRAM) macro in 3D Nanofabric process technology. The objective is to create an SRAM macro that exhibits enhanced performance and efficiency compared to 2D and alternative 3D integration approaches.

This project provides an excellent opportunity for students to gain practical experience in semiconductor design, advanced circuit fabrication, and cutting-edge memory technologies. It will also enhance their understanding of the challenges and opportunities associated with 3D integration and SRAM design in the context of future advancements in CMOS process technology.

Required background: Good programming skills, and knowledge of Analog and Digital circuit design 

Supervisors: David Novo (david.novo@lirmm.fr), Pascal Nouet (pascal.nouet@lirmm.fr), and Dawit Abdi (dawit.abdi@imec.be)