AI-based PDK-aware power modeling flow for computing architectures

The compute stack—from devices to software—is the largest and fastest-growing consumer of IT energy. To achieve energy-efficient computing, designing new circuits and architectures is essential, especially as technologies like CMOS, memory, and interconnects evolve. CPUs and Domain Specific Architectures (DSAs) play a key role by tailoring hardware to specific tasks, improving energy efficiency at both instruction and application levels. 

However, optimizing these architectures is time-intensive due to lengthy design and simulation cycles. Traditional energy evaluation methods require a full ASIC design flow, which delays time to market for complex DSAs. While faster analytical models exist, they often lack accuracy. This challenge is amplified by the need for Design and Technology Co-optimization (DTCO), where designers and process engineers collaborate to enhance power efficiency while reducing development time and cost. 

The aim of this work is to leverage artificial intelligence for decreasing the DSA energy evaluation time to market and providing a quick PDK-aware power prediction flow. The use cases of the proposed work will be both in technology benchmarking for power related TCO factors and system level energy efficiency evaluations. This flow also can help improving existing EDA flows for energy efficiency optimization. 

To this end, a framework will be developed throughout this PhD thesis that will characterize the target computing architecture in terms of design and sub-component activities across various workloads. This characterization will leverage advanced technology nodes (PDKs) available at imec, using the in-house Physical Implementation Flexible Framework. The resulting flow generates a technology-dependent dataset for training a power model, which also serves as a valuable benchmark for process technologies. Additionally, the characterization enables efficient learning of diverse workloads within short simulation times. 

The proposed framework leverages advanced machine learning techniques to make the benchmarking and modeling flow fast and efficient. The trained model will be a high-level that can fit in existing virtual platforms for system level design space exploration, system power management, DVFS, etc.  

Master of Science degree in electrical engineering or equivalent  

Strong knowledge in digital system design, including HDL design, simulation and synthesis. 

Experience and be practical with Python. 

Experience with Conventional EDA design flow tools for characterization flow.  

Knowledge on PDKs and device level experience is a plus advantage. 

Knowledge on machine learning technique is a plus advantage. 

Strong interest in cross collaboration between working teams; System Architecture, PDK, DTCO and Software and Algorithm 

You combine a strong interest in engineering and scientific research with a desire to see your work applied (in industrial, academic or (N)GO collaboration). 

You aspire to become an expert in your field, while simultaneously collaborating with other researchers and senior staff to efficiently generate state-of-the-art results.