Automated electrical characterization for emerging transistor architectures

A circuit idea is only as real as its layout. Between a circuit description and a verified, characterized building block lie placement, routing, design-rule and layout-versus-schematic checks, parasitic extraction and characterization, steps that are still largely manual for anything new and that differ from one transistor architecture to the next. This is where most promising ideas stall, and where the models that proposed them meet their first real test.

The student will work on automating the physical realization of digital building blocks on open process design kits with open layout, verification and simulation tools: layout generation driven by the circuit's structure, the verification and extraction chain, characterization to industry-standard formats, and a systematic comparison of the realized result with the models that predicted it, so that the models can be corrected where they miss.