Automated multi-constraint routing for spin-based quantum processor architectures

Advances in semiconductor quantum technologies increasingly rely on densely integrated arrays of gate-defined quantum dots for spin‑qubit processors. A critical bottleneck in scaling these architectures is the automated routing of the complex, multi‑layer wiring networks required to interface nanoscale gate electrodes with micrometer‑scale contact pads. This project aims to develop a high‑performance auto‑routing framework tailored to the unique constraints of quantum‑dot spin qubit devices. The student will investigate algorithmic strategies for simultaneously routing large numbers of wires that must remain non‑crossing, satisfy stringent spacing rules, and gradually transition in width by more than an order of magnitude along their routing path, from tens of nanometers at the qubit layer to several micrometers at the periphery.

This project is at the intersection of computational optimization and state-of-the-art quantum-processor design in collaboration with the spin-qubit research group at imec.

Emphasis will be placed on modeling manufacturability constraints, developing efficient search heuristics, and validating routing performance on realistic quantum‑processor layouts.