Cell-to-cell disturb in 3D FeFET with Oxide-Semiconductor channel

Motivations

Vertically stacked ferroelectric FETs (3D FeFETs) are attracting increasing interest thanks to their non-volatility, high speed, low energy consumption, and high density.

In addition, the oxide–semiconductor channel enables high‑endurance operation, making 3D FeFETs strong candidates for future high‑bandwidth memory solutions.

However, several device aspects are still under investigation. One critical topic is cell‑to‑cell disturb, which may occur during standard read and write operations.

The goal of this internship is to assess the severity of these disturb mechanisms and to evaluate potential mitigation strategies.

Objectives

The selected candidate will be involved in the following research activities at imec:

1. Electrical characterization of 3D ferroelectric capacitors and FETs
   (IV sweeps, PV/PUND measurements, cycling, endurance testing)
2. Development of procedures to assess read/write cell‑to‑cell disturb during standard 3D FeFET operation.
3. Evaluation of disturb mechanisms across different material stacks and proposal of mitigation techniques.

Requirements:

1. Background in Electrical engineering, semiconductor physics, semiconductor device reliability.
2. Fundamental knowledge of ferroelectric devices.
3. Previous experience with electrical characterization of ferroelectric devices (FeFET and FeCAP).
4. Internship up to 8 months year, self-supported