/Charge trapping in advanced CMOS devices at cryogenic temperatures for quantum computing applications

Charge trapping in advanced CMOS devices at cryogenic temperatures for quantum computing applications

PhD - Leuven | More than two weeks ago

Unravel fundamental reliability physics to enable large-scale quantum computing

Over the past decades, the continued demand for increasing computing power has fueled the growth and evolution of the mainstream CMOS technology. Physical device scaling, which stood at the basis of this growth, is eventually approaching fundamental physical barriers, triggering the search for viable alternative computing concepts. One of the most promising concepts is quantum computing, which emerges rapidly as a research field that has the potential to bring to practice technologies exploiting massive parallelism and to push the computational power way beyond the contemporary realm.

 

Because of fundamental limits to the tolerable operating temperature of qubits, one major hurdle towards large-scale integration is their interface to the classical control circuitry required for operating them. A promising approach to overcome this problem is to deploy traditional CMOS circuitry in cryogenic environments for efficient operation of future quantum computers by reducing limitations due to wiring and signal integrity.

For the design of CMOS circuits at such low temperatures, classical transistor models often fail to capture important physical mechanisms such as the effects of band-tail states, tunneling, or mechanical strain. Recent studies also highlighted the fundamental importance of charge noise on the decoherence times of spin-based qubits, creating additional interest for a deeper understanding of charge trapping related phenomena like random telegraph noise, bias temperature instability and hot-carrier degradation. These effects are traditionally thought to be strongly temperature activated and would therefore be expected to freeze out at low temperatures. However, recent experimental studies have reported an unexpected weakening of the temperature dependence of charge trapping at cryogenic temperatures, suggesting the need of a fundamental revision and expansion of classical models.

The candidate therefore should develop an accurate physical understanding of defect generation (bond dissociation) and charge trapping effects and their influence on CMOS devices from room temperature to liquid Helium temperatures and below. Close interaction with circuit design and quantum computing teams will help to continuously improve ASICs specifically targeted to operate qubits, but also the quality and integration of spin-based qubits. Furthermore, the candidate should explore the limits of traditional defect generation and charge trapping models and help to improve our understanding of the physics of advanced MOS stacks at cryogenic temperatures.

Charge trapping in advanced CMOS Threshold voltage drift as a function of gate and drain bias at different temperatures. Each dot in the maps represents data extracted from 50 similar devices, which roughly is equivalent to a 2-sigma interval. Note that the degradation does not only not freeze out at low temperatures, but even increases for certain bias conditions at lower temperatures.

 

Required background: semiconductor physics, programming experience (preferably Python), transistor reliability, knowledge in TCAD and in electrical measurements of transistors are a bonus

 

Type of work: 40% electrical characterization of CMOS devices at various temperatures, 40% data analysis and modeling, 20% literature

Supervisor: Valeri Afanasiev

Co-supervisor: Stanislav Tyaginov

Daily advisor: Alexander Grill, Arnout Beckers

The reference code for this position is 2022-015. Mention this reference code on your application form.