Charge trapping in advanced CMOS devices at cryogenic temperatures for quantum computing applications

Because of fundamental limits to the tolerable operating temperature of qubits, one major hurdle towards large-scale integration is their interface to the classical control circuitry required for operating them. A promising approach to overcome this problem is to deploy traditional CMOS circuitry in cryogenic environments for efficient operation of future quantum computers by reducing limitations due to wiring and signal integrity.

For the design of CMOS circuits at such low temperatures, classical transistor models often fail to capture important physical mechanisms such as the effects of band-tail states, tunneling, or mechanical strain. Recent studies also highlighted the fundamental importance of charge noise on the decoherence times of spin-based qubits, creating additional interest for a deeper understanding of charge trapping related phenomena like random telegraph noise, bias temperature instability and hot-carrier degradation. These effects are traditionally thought to be strongly temperature activated and would therefore be expected to freeze out at low temperatures. However, recent experimental studies have reported an unexpected weakening of the temperature dependence of charge trapping at cryogenic temperatures, suggesting the need of a fundamental revision and expansion of classical models.

The candidate therefore should develop an accurate physical understanding of defect generation (bond dissociation) and charge trapping effects and their influence on CMOS devices from room temperature to liquid Helium temperatures and below. Close interaction with circuit design and quantum computing teams will help to continuously improve ASICs specifically targeted to operate qubits, but also the quality and integration of spin-based qubits. Furthermore, the candidate should explore the limits of traditional defect generation and charge trapping models and help to improve our understanding of the physics of advanced MOS stacks at cryogenic temperatures.