/Design-Space Exploration of a Non-volatile computing framework for distributed processing at the Edge

Design-Space Exploration of a Non-volatile computing framework for distributed processing at the Edge

Leuven | More than two weeks ago

Leveraging non-volatile memories on applications and circuits to maximize energy efficiency on edge devices.

Human Computer Interaction has taken a leap forward in the past decade with the advent of advanced software and hardware infrastructure and will dominate edge computing or distributed on-sensor computing paradigm for the coming years. High quality digital pixel sensors, emerging network connectivity, advent of computer vision (CV) and artificial intelligence (AI) algorithms and low-power domain-specific accelerators have funnelled the growth of virtual reality (VR) and augmented reality (AR) platforms. Advanced pixel sensors and hybrid integration technologies are resulting in a reduced form factor sensor-processor infrastructure, facilitating the growth of AR systems. For on-chip/sensor distributed computing, some of the key system requirements are: minimal data movement and latency between sensor and compute block, low-complexity hand/eye tracking and AI algorithms, an efficient memory hierarchy, pipelined micro-architecture with respect to the dataflow and communication bandwidth, among many other factors.


Energy saving strategies during active and inactive phases are a key factor in such distributed systems in comparison to traditional centralized computing systems. The mapping of the logic, in terms of optimal partitioning of the image processing pipeline over the distributed compute architecture is one of the essential contributors to energy optimisation. Similarly, non-volatile memories have an important role to counter SRAM leakage and high on-chip storage requirements for complex deep neural network (DNN) processing. Emerging non-volatile memories eradicate leakage while promising denser arrays placed next to the computing element, or even replacing it, viz. computation in/near memory. MRAM technology is being widely explored with many variants – STT, SOT and VGSOT which could have an impact in memory access metrics for system performance. Spin Transfer Torque (STT) and Voltage Gate controlled Spin Orbit Torque MRAM memories are the candidates to replace storage-class arrays as well as cache-class memories, but more importantly, their characteristics enable innovative near/in-memory architectures to process the sensor data. Furthermore, even more radical concepts arise: non-volatile elements in the data-path promise state-retention elements, and new ways of computing boolean functions, from basic NAND/NOR gates to complex binary queries. A dedicated energy management strategy is needed to capture computation workloads, the underlying dataflow, dynamic reconfigurability for mapping DNN layers to available compute resources, memory subsystem requirements and corresponding mapping to hardware resources.


The aim of this Ph.D. is three-fold: 1) performance and energy modelling for AR/VR workloads considering distributed on-chip compute and several design factors as stated above, 2) propose non-volatile computing framework comprising hybrid memory organisation (NVM with SRAM) and non-volatile logic for DNN processing; 3) analyse workload aware configurations of the proposed framework based on optimization of the design parameters.

Required background: Master’s degree in electrical engineering or Computer Engineering

Type of work: 10% literature study, 25% computer architecture, 25% performance modelling, 40% digital design

Supervisor: Marian Verhelst

Daily advisor: Leandro M. Giacomini Rocha, Fernando Garcia Redondo, Dwaipayan Biswas

The reference code for this position is 2024-036. Mention this reference code on your application form.

Who we are
Accept marketing-cookies to view this content.
Cookie settings
imec's cleanroom
Accept marketing-cookies to view this content.
Cookie settings

Send this job to your email