DTCO modeling framework enabling CMOS2.0 technology pathfinding

Advanced technologies are pushing the limits of both design and technology capabilities, resulting in complex device architectures to achieve ever better power, performance and area (PPA) trade-offs. Pathfinding research on these advanced technologies requires precise modeling at different abstraction levels. Nevertheless, every abstraction level creates boundaries. Ideally, the impact of these boundaries should be negligible. However, when scaling down, these boundaries may significantly impact PPA trade-offs. Especially as we move towards CMOS2.0, where we further scale these boundaries, actively modeling boundaries is key for pathfinding research.

In this PhD, you will assess the existing Design-Technology Co-Optimization (DTCO) modeling flow at different abstraction levels, studying the impact of potential inaccuracies. Varying different boundary conditions, you will evaluate the impact of the boundaries on PPA trade-offs.

You will build an extended DTCO modeling framework, meticulously addressing boundaries, to enable CMOS2.0 technology exploration. Using this modeling framework, you will optimize devices and technologies progressing towards the CMOS2.0 era.