Extension of the In-house Simulation Framework for Emerging Memory Technologies as Buffer Memory

Modern applications demand larger memory capacity and higher bandwidth at lower power price. However, while the current memory technologies are approaching their scaling limit, it is becoming more challenging to meet the demand cost-efficiently. This situation calls for alternative memory interface technologies and memory subsystem architectures (e.g., Compute Express Link (CXL)) using more advanced technologies for memory organization and communication to improve memory capacity and bandwidth with lower cost. System-level simulations of such alternatives are of paramount importance in early-stage design space exploration.
During the internship, you will work with existing in-house system-level CXL framework, extending it for novel memory technologies, such as 2TNC FeRAM, 3D FeFET, and 3D CCD. You will evaluate the new technologies against state-of-the-art solutions, using emerging AI workloads.

Objectives:

• Extend existing CXL framework to incorporate advanced memory technology
• Analyse the impact new memory features on system performance and energy efficiency
• Simulate and validate the enhanced framework using representative AI workloads
• Enable early-stage design space exploration of CXL-connected buffer memory based on variety of memory technologies

Skills to stand out:

• Strong programming skills in C++ or Python
• Solid understanding of memory subsystem
• Familiarity with different bit cell concepts
• Experience with performance modelling techniques
• Exposure to system-level simulation tools or benchmarking frameworks is a plus (Ramulator, DRAMSys, DRAMSim, Gem5, …)

Type of Project: Internship

Master's degree: Master of Engineering Science; Master of Science

Duration: 3-6 Months

For more information or application, please contact the supervising scientist Khakim Akhunov (khakim.akhunov@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.