Gate Stack Engineering for 2D FETs Using Through-Dielectric Ionic Currents

Two-dimensional semiconductors such as MoS₂ and WSe₂ are promising candidates for future electronic technologies due to their atomic thickness and excellent electrostatic control. However, the integration of (high-k) gate dielectrics, an essential component of transistor operation, often introduces defects at the dielectric/semiconductor interface. These defects degrade carrier mobility, increase trap densities, and reduce device reliability, creating a major obstacle to the adoption of 2D semiconductors in next-generation electronics.

This PhD project explores a fundamentally new approach to interface engineering. Rather than focusing on preventing defect formation during fabrication, the project investigates whether defects can be repaired after gate-stack formation through controlled ionic transport across ultrathin gate dielectrics. By combining electrochemistry, ionics, materials science, and transistor technology, the research aims to establish a new methodology for post-fabrication defect engineering in advanced semiconductor devices.

The candidate will develop electrochemical processing techniques, characterize dielectric and interface defects, investigate ionic transport mechanisms through gate stacks, and translate the resulting insights into improved performance and reliability of 2D transistor devices. Success could establish ionic engineering as a powerful new tool for controlling interfaces and enhancing the functionality of future semiconductor technologies.