High-density communication for chiplet applications in sub-µm pitch packaging technologies

High-density communication for chiplet applications in sub-µm pitch packaging technologies.

In recent years, the semiconductor industry has been defining a new paradigm in the design and fabrication of integrated circuits and moving away from the traditional monolithic approach, where a single die contains all functionalities. Instead, the system is partitioned into several chiplets each with specific functionalities. The chiplets are interconnected and integrated with advanced packaging technologies such as silicon interposer/bridge or polymer-based ReDistribution Layer (RDL).

However, while chiplet-based architectures offer numerous advantages, they also introduce new challenges, particularly in terms of interconnectivity, reliability, and power delivery. Efficient communication and data exchange between chiplets within a package are critical for ensuring the overall system's performance and functionality. Also, chiplets architecture necessitates the transmission of large volumes of data reliably between different functional units, such as processors, memory modules, accelerators, and I/O interfaces.

What you will do:

• Review of chip-to-chip interconnect architectures and investigate the requirements and challenges specific to high-density chiplet communication in advanced packaging technologies.
• To design, simulate high-density communication links optimized for chiplet applications in sub-µm pitch packaging technologies.
• Compare interconnect (microstrip, grounded CPW, striplines, …) and power delivery strategies (e.g., the impact of integrated mimcap).
• Develop and measure a test-chip in an advanced technology node
• Evaluate the performance of the proposed communication links in terms of bandwidth, power efficiency, latency, and reliability.
• Publish and present results both at international conferences and in scientific journals.
• You will be involved in different research projects related to your PhD topic and collaborate with research partners from industry.

Who you are:

• Holder of a master’s degree in electronic engineering, 
• Strong interest in SoC design
• Strong analytical skills for designing and implementing abstract models.
• You work independently, have a strong feeling of responsibility, and are able to commit to timing and milestones set forward by different research projects.
• You are a team player and have strong communication skills.
• Good knowledge of English (oral and written)

Supervisor: Peter Ossieur

Daily advisors: Nicolas Pantano, Marko Simicic