Master projects/internships - Leuven | More than two weeks ago
Take part in the optimization of the next logic devices while getting acquainted to all steps of the optimization chain: from technology choices, to electrical characteristics then to library place and route.
Continuous scaling of logic technologies requires the investigation of new transistor and circuit designs. The optimization of device and technology options together with circuits and systems is more than ever essential. To assess future technology options, TCAD tools are used to assess device and interconnects and to enable circuit simulations.
To design the logic circuit, a full library of standard cells is designed, implementing all required boolean functionalities (from a basic inverter up to a full-size flip-flop). Due to the design complexity of larger systems, a place-and-route tool is used which governs the placement and interconnection between the chosen cells. In order to provide this place-and-route tool with the behaviour of each standard cell under different signal and load conditions, each standard cell must be passed through a TCAD tool that extracts the cell’s parasitic R&C netlist. Each cell’s power and performance are then evaluated using a spice benchmark under various signal and load conditions. This is called library characterization.
What you will do
During this internship, you will use a third party TCAD tool to perform full library netlist extraction and contribute to the development of a spice benchmark for library characterization. You will also be involved in the integration of this third party TCAD tool in imec’s existing infrastructure. You will be exposed to digital circuit design and technology evaluation. You will be implement new benchmarks and process TCAD simulation data. You will work in the device modelling team. You will be guided in your work and be involved in interactions with the TCAD tool vendor.
The tasks include:
Who you are
Type of Project: Internship
Master's degree: Master of Engineering Technology
Duration: 4 months
Master program: Electrotechnics/Electrical Engineering
Supervising scientist: Pieter Schuddinck
For more information or for application, please contact Marie Garcia Bardon (firstname.lastname@example.org)
Imec allowance will be provided.