/Modeling and evaluating the CXL.mem pooling

Modeling and evaluating the CXL.mem pooling

Leuven | More than two weeks ago

Implement a simple SST model supporting CXL.mem to achieve accurate latency / bandwidth simulation
This Master's thesis/Internship proposal explores the transformative capabilities of CXL.mem pooling, focusing on the convergence of compute and memory resources. By modeling and evaluating CXL.mem, this research aims to uncover its theoretical underpinnings, assess its practical implications, and provide valuable insights for optimizing memory architectures in data-intensive applications. Through a comprehensive exploration, this study seeks to contribute to the evolving landscape of high-performance computing and data-centric applications.

Month 1: Literature Study (15%)

Define Objectives and Scope

In-Depth Literature Review

Month 2-4: Framework Development/performance modeling (50%)

Understanding Framework Design and Architecture

Implementation of SST Model supporting CXL.mem


Month 5: Evaluation (25%)

Define Evaluation Metrics

Simulation and Testing


Month 6: Reporting and Documentation (10%)

Results Analysis and Discussion

Final Report Writing

Presentation [and Submission]

Type of project: Internship

Duration: 6-9 months

Required degree: Master of Engineering Technology

Required background: Electrotechnics/Electrical Engineering, Computer Science

Supervising scientist(s): For further information or for application, please contact: Saeideh Alinezhad Chamazcoti (Saeideh.alin@imec.be)

Imec allowance will be provided.

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