Modeling and optimization of multi-chiplets package

In recent years traditional CMOS scaling has been slowing down due to inherent physical and technological limitations to Moore’s law. Excessive shrinking of the device size has led to leakage currents becoming a restrictive factor in terms of performance. Similarly, high metal resistance induced by scaled interconnect dimension are highly detrimental for block-level signal distribution and timing. Complementary to these limits, modern applications such as AI algorithms and automotive solutions require massive number of resources in terms of memory, bandwidth, and redundancy. Accommodating these requirements in hardware brought an explosion of multi-core systems, with many CPUs and GPUs in the same System on Chip (SoC). Manufacturing all these components monolithically in the same package is, however, unfavorable as it would require large area and, consequently, high cost.

Stacking chips in the same package (3D) and a multi-chiplet system with silicon interposer on the same package (2.5D) are emerging in the industry as solutions to overcome these problems and engineer the next generation of SoCs.

Splitting a conventional 2D SoC into many different functional blocks allows the designer to leverage standard communications modules such as PCIe, or HBM, as well as different types of substrates to achieve very high bandwidth between different chiplets. Additionally, different 3D integration techniques can be combined in the same SoC to achieve peak PPA performance both at the single-chiplet and multi-chiplets level. Naturally, this also comes with existing challenges, related for instance to the difficulty to perform top-level system planning, and co-design of the individual dies and the package, as well as the struggle to realistically model power and thermal behavior of the system.

The goal of this project is to tackle these challenges by performing early-stage Power, Performance, Area, and Cost (PPAC) analysis of a multi-chiplets package combining multiple open-source logic, memory, and interconnect modules. To do so the student will have to work on modeling different SoC configurations, and then run system-level power, timing, and thermal simulations to explore design trade-offs. This will be achieved by using in-house analytical models and/or commercial EDA tools, relying also on IMEC’s wide expertise in technology, design, and system architecture. Prior knowledge on semiconductor manufacturing processes and basic knowledge of digital design is useful, though not mandatory.

A summary of the work split is as follows:

• 10% literature study and tools learning
• 20% summary implementation of open-source modules
• 40% modeling of different SoC configurations
• 30% early-stage system-level PPA analysis

Reading material:
• “Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling” - S Bhattacharya et. Al. – 2023 Symposium on VLSI technology and circuits
• “Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)” – S.-P. Jeng and M. Liu – 2022 International Electron Device Meeting (IEDM)
• “Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families” – S. Naffziger et al. – 2021 International Symposium on Computer Architecture (ISCA)
• “An Integrated System Scaling Solution for Future High-Performance Computing” – C.-H. Tung and D. Yu - 2023 Symposium on VLSI technology and circuits
• “Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits” – G. H. Loh et al. – 2021 Design, Automation & Test in Europe conference (DATE)

Type of Project: Combination of internship and thesis, Internship

Master's degree: Master of Science/Engineering Technology

Master program: Electrical Engineering

Duration: 6 months

For more information or application, please contact Giuliano Sisto (giuliano.sisto@imec.be)