[NanoIC] Design-Technology Co-Optimization for embedded and heterogeneously integrated devices in future semiconductor systems
PhD - Leuven | Just now
Device heterogeneity in future semiconducting systems challenges design-technology co-optimization research to look beyond pinpointing a complex device architecture with an optimal power, performance, and area (PPA) trade-off. Pathfinding research for future semiconductor systems requires not only meticulously tailoring trade-offs towards the envisioned application, but also diversifying trade-offs within one application. As different subcircuits within one application, e.g., a CPU, could benefit different trade-offs, enabling significant differences in technology within on application, addressing these trade-offs for subcircuits individually is key for pathfinding research.
In this PhD, you will explore, model, and/or optimize emerging device architectures for future semiconductor technologies, including both advanced CMOS and beyond-CMOS devices. The core of the PhD is a cyclic Design-Technology Co-Optimization (DTCO) methodology. Rather than following a strictly sequential process, the methodology is iterative, allowing results obtained at later stages to guide additional device modeling and optimization efforts.
During the first phase of the research, you will focus on the conception, development, and evaluation of a novel transistor architecture based on shared n-type and p-type nanosheet channels. The proposed architecture aims to improve area efficiency and reduce parasitic capacitances while remaining compatible with future heterogeneous integration paradigms such as CMOS 2.0 and τ-scaling.
Throughout this PhD, you will develop a multidisciplinary skillset, starting with a detailed physics based TCAD study. Further, process emulation inputs, layout insight, compact modeling, and detailed parasitics analysis are key factors in cell level modeling and optimization. You will use these cell level models to benchmark different device and technology options for multifarious design points. Based on your assessments, you will optimize a set of devices and technologies progressing towards heterogeneously integrated semiconducting systems.
Required background: Nanotechnology, Electrical Engineering or equivalent.
Type of work: 60% modeling/simulation, 25% design, 15% literature
Supervisor: Devin Verreck (KU Leuven)
Co-supervisor: Devin Verreck (KU Leuven)
Daily advisor: Sheng Yang
The reference code for this position is 2027-182. Mention this reference code in your application.