[NanoIC] Reliability characterization of CMOS 2.0 nodes using low-frequency noise​ ​

What you will do

To continue to increase the functionality per unit area, the semiconductor industry is moving towards a CMOS 2.0 architecture, where memory and logic functions are brought together into one platform. This architecture entails millions to billions of closely connected state-of-the-art devices that have to survive long and complex integration. The integration challenges together with the nanoscale dimensions of the devices introduces important reliability challenges.

In this PhD project, you will investigate low-frequency noise (LFN) as a sensitive and non-destructive tool for reliability characterization of CMOS 2.0 technologies. The goal is to establish a fundamental understanding of the relationship between noise and key degradation mechanisms, including Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB).

Your research will combine electrical characterization, data analysis, and physics-based modeling to answer fundamental questions:

• How is device noise linked to reliability degradation?
• Can noise measurements be used to predict device lifetime and failure?
• Which physical mechanisms govern gate and drain current noise in CMOS 2.0 devices?

The work will involve characterization of state-of-the-art transistor technologies, development of novel reliability characterization methodologies, and creation of physics-based models that connect noise signatures to degradation mechanisms.

This PhD position is based in the Device Reliability team at imec in Leuven, Belgium, and is conducted in collaboration with KU Leuven.

What we do for you

• A fully funded PhD position at imec with competitive salary.
• Access to state-of-the-art technologies and advanced characterization infrastructure.
• Close collaboration with experts in device physics, reliability, and CMOS technologies.
• Opportunities to publish in leading international journals and present at major conferences.
• An international and multidisciplinary research environment in Leuven, Belgium.

Who you are

• You hold, or will soon obtain, an MSc degree in Electrical Engineering, Physics, Microelectronics, Materials Science, or a related discipline.
• You have a strong interest in semiconductor physics.
• Experience with programming and data analysis (Python, MATLAB, or similar) is a plus.
• You have strong written and spoken English communication skills.

References

1. R. Asanovski et al., Wafer-Level 1/f Noise Characterization of Scaled P-Type Nanosheets and Comparison with Planar HKMG Transistors, IEEE International Reliability Physics Symposium (IRPS), 2026.
2. R. Asanovski et al., Impact of Gate Metal Work Function on 1/f Noise in RMG MOSFETs, IEEE International Reliability Physics Symposium (IRPS), 2025.
3. R. Asanovski et al., Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal-Budget RMG MOSFETs Using 1/f Noise Analysis, IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 1745-1751, 2024.
4. Y. K. Chang et al., Exploring AC Time-Dependent Dielectric Breakdown (TDDB) Through Frequency Noise Analysis, IEEE International Reliability Physics Symposium (IRPS), 2025.