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/[NanoIC] Revealing Yet-Unknown Manufacturing Defects in Advanced Semiconductor Technologies

[NanoIC] Revealing Yet-Unknown Manufacturing Defects in Advanced Semiconductor Technologies

PhD - Leuven | Just now

Combining design, manufacturing, and test
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Technology keeps scaling down: in the few years we have moved from the nanometer domain to the angstrom domain. These advanced technologies show (1) increased sensitivity for subtle manufacturing defects and, as the complexity of the circuits we can design in these advanced technologies keeps on increasing, (2) the number of potential fault locations increases as well.
 
 
IC technology is increasingly applied in domains where test escapes cannot be tolerated. In the automotive domain, customers use the term “zero defects”, which explicitly refers to their zero-tolerance for test escapes (i.e., faulty chips that nevertheless pass all tests). If, say, an airbag controller goes off due to a test escape, the financial, legal, and reputation damage can hardly be exaggerated. The same is true in applications like medical, avionics, and data centers. In the latter, test escapes cause “silent data corruption’’.
 
 

The objective of this project is to identify new defect types and behaviors and their detection conditions for advanced semiconductor technologies. If their nature so demands, we should develop new fault models and corresponding ATPG (automatic test pattern generation) detection algorithms, such that future products that are based on these technologies can be tested for them.

Methodology/workplan

Design a functional test chip in an advanced technology (for example based on a RISC processor with peripherals, as was done in another project at TU Delft). We will involve imec IC Link for the final chip finishing and layout. We intend to manufacture this IC design at a commercial foundry, e.g., TSMC. We will design certain defects into this chip. Also, we plan to include a network of embedded test instruments into the chip design, such as various types of embedded sensors (for temperature, toggle counters, voltage drop, etc.) that can be read out while the test chip continues to run in its functional mode. In this way, we hope to learn more about the nature of the defects.

 

Tests will be generated for all known fault models. With the from imec IC link, we will run the various tests at the Teradyne UltraFLEXplus.

 

This project is a cooperation between imec EOTS and TU Delft. Prof.dr. Said Hamdioui will act as promotor and Erik Jan Marinissen is the scientific responsible. Other parties which will be involved are.

  • Imec IC Link: Chip layout and finishing; getting tests to run at Teradyne ATE
  • Phil Nigh (ex-Broadcom): External consultant
  • Bram Kruseman (NXP Semiconductors): External consultant


 


 


 


 

Required background: Computer science, Electrical Engineering, Engineering Science, Physics

Type of work: 20% design, 20% ATPG/simulation, 40% experimental, 10% literature, 10% publications

Supervisor: Said Hamdioui (TU Delft)

Co-supervisor: Said Hamdioui (TU Delft)

Daily advisor: Po-Yao Chuang

The reference code for this position is 2027-119. Mention this reference code in your application.

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