Neural stimulator in a standard CMOS technology

Neurostimulation has evolved into a foundational technology, playing a pivotal role in advancing the development of closed-loop neural interfaces and presenting a promising therapeutic avenue for a wide array of neurological disorders. One of the common challenges faced in the design of neurostimulators is the integration of components tailored for high-voltage stimulation with those optimized for low-voltage recording.

Traditionally, neurostimulators have made use of Bipolar-CMOS-DMOS (BCD) technology, a versatile technology well-suited for accommodating the diverse requirements of power devices in high-voltage applications. However, the implementation of BCD technology introduces a potential drawback in the form of an integration penalty.

Recognizing the need for a comprehensive solution, the adoption of a CMOS-compatible stimulator architecture emerges as a critical advancement. It also allows for the seamless integration of high-voltage and low-voltage components on a single chip. This integration not only addresses the challenges posed by the integration penalty but also contributes to a more compact, energy-efficient, and versatile neurostimulator system.