Neuromorphic computing primitives in advanced CMOS technologies

Abstract:

The development of advanced neuromorphic systems demands hardware that can emulate the functional principles of biological neural networks with far greater efficiency than conventional digital architectures. While algorithmic innovations have enabled significant progress in brain-inspired computing, their performance is ultimately constrained by the underlying device-level primitives.

Research into neuromorphic functionality directly at the hardware level—such as in nanoscale transistors, or emerging memory devices/resistive elements—is therefore critical for overcoming the energy, latency, and scalability bottlenecks of current designs. By tailoring device characteristics to inherently support neural operations like plasticity, temporal dynamics, and event-driven computation, it becomes possible to unlock orders-of-magnitude improvements in efficiency and enable neuromorphic systems that are not only faster and more compact, but also capable of operating closer to the biological regime they seek to emulate.

The efficient realization of neuromorphic systems requires primitives that can reproduce neuronal spiking dynamics at the level of individual devices and small circuit blocks. Transistor devices and CMOS-compatible building blocks offer a natural foundation for this effort, as they can be configured to emulate critical neural features such as thresholding, integration, spiking, and refractory behavior with high fidelity. Identifying, developing and benchmarking such primitives is essential to move beyond purely algorithmic models, enabling hardware that embodies spiking functionality at its core. This work focuses on device-level research to assess trade-offs in energy consumption, latency, variability, and scalability, ultimately shaping out the design of fundamental building blocks for use in neuromorphic architectures that can operate efficiently across a wide range of computing tasks.

In addition to neuron primitives, synaptic functionality at the device and array level is equally crucial for enabling efficient neuromorphic computation. Large-scale memory arrays provide a natural platform for implementing synaptic weights and connectivity, but current digital memory architectures are not optimized for the analog, dynamic, and massively parallel operations required in spiking networks. This work will explore how memory elements, ranging from SRAM/DRAM cells to emerging non-volatile memories, can be tailored or co-designed to express synaptic behaviors such as plasticity, stochasticity, and long-term retention, while remaining compatible with advanced CMOS integration. Such efforts would eventually enable blending of storage and computation, thereby reducing data movement bottlenecks that dominate conventional von Neumann systems.

The research will leverage test device structures fabricated in advanced CMOS logic and memory technologies to explore paths for emulating neuromorphic neuronal and synaptic behavior by identifying new device operation modes. Generic test structures will be extensively characterized electrically using imec’s advanced measurement infrastructure, offering high-throughput characterization with time resolution down to the nanosecond scale. The insights gained will be used to model, simulate, design, and test small building blocks that can be optimally operated to perform neural and synaptic functions. This approach will establish a systematic pathway from device-level exploration to circuit-level neuromorphic functionality, ultimately contributing to the foundation of scalable and energy-efficient neuromorphic systems design.

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Profile:

We are looking for an enthusiastic person with a background/MSc degree in physics or electrical engineering, to join our team and carry out research on neuromorphic computing hardware. Furthermore, you:

• Have solid theoretical knowledge and very good device physics understanding
• Have basic exposure to electrical characterization techniques and are willing to broaden and perfect your skills in this area
• Understand device operation and circuit techniques beyond the digital domain
• Are familiar with programming environments (Matlab, Python, etc), device and circuit simulators
• Have a good knowledge of CMOS technology
• Are willing to publish your best results in top-level conferences and/or high-impact journals in the field
• Are able to think out-of-the-box and can easily approach areas outside your comfort zone
• Can adapt and are able to reconsider your approach dynamically, while taking into account concurrent/new developments; you strive for the best
• Are a self-driven person, able to work independently, while placing your work in the context of a larger team effort and organization’s strategic needs and priorities
• Can work in an interdisciplinary team, including device and process engineers, simulation and reliability experts, materials scientists; are engaged, dependable and flexible
• Have good communication, presentations and writing skills; like working in an international and multicultural environment; are fluent in English

References:

1. S. Pazos et al: “Synaptic and neural behaviors in a standard silicon transistor”, Nature 640: 69–76 (2025)
2. J.-K. Han et al: “Cointegration of single-transistor neurons and synapsesby nanoscale CMOS fabrication for highly scalable neuromorphic hardware”, Sci. Adv. 7, eabg8836 (2021)
3. Y. Chen et al: “A compact artificial spiking neuron using a sharp-switching FET with ultra-low energy consumption down to 0.45 fJ/spike.” IEEE Electron Device Lett. 44, 160–163 (2023).
4. H. Kim et al: “Spiking Neural Network Using Synaptic Transistors and Neuron Circuits for Pattern Recognition With Noisy Images”, IEEE Electron Device Lett. 39, 630-633 (2018).
5. M. Jerry et al: “A ferroelectric field effect transistor based synaptic weight cell”, J. Phys. D: Appl. Phys. 51, 434001, 2018.