Event-Driven Neuromorphic IC Architectures for Energy-Efficient Implantable Biosensing

Implantable biosensors offer a transformative approach to health monitoring, providing real-time insights into physiological states. However, the success of such systems hinges critically on a highly integrated, low-power design and the capability for processing complex biological signals in situ. Additionally, multi-panel sensing arrays capable of detecting diverse biochemical signals simultaneously, require processing of multiple data streaming efficiently while maintaining ultra-low power consumption for implantable use.

At Centre for Microsystems Technology (CMST), an imec associated research lab at Ghent university, and through the ERC Starting grant NEFELI, we are developing neuromorphic sensors based on memristors, that leverage brain-inspired architectures to enable energy-efficient, real-time sensing and processing of biochemical physiological signals at the sensor level, reducing the need for power-hungry computation. For integration and reliability of the entire implantable electronic system, neuromorphic biosensors benefit significantly from Application-Specific Integrated Circuit (ASIC) that enables the hardware implementation of event-driven processing architectures, supporting in-memory computation, local learning rules, and analog signal conditioning, all critical for real-time responsiveness and minimal latency. This PhD research topic will pioneer the development of an integrated ASIC tailored for multi-panel implantable biosensors with neuromorphic processing capabilities drastically reducing power consumption and improving data interpretation. It paves the way for advanced medical devices with applications in disease management.

Scientific challenges

• Design and develop an application-specific integrated circuit (ASIC) biosensor front-end for multi-panel electrochemical sensing, enabling simultaneous acquisition from multiple sensor sites. The work will involve comprehensive electrical characterization of the sensor array, development of quantitative models to guide front-end architecture, and integration of analog front-end (AFE) circuitry, data converters, power management, and wireless telemetry modules optimized for implantable biomedical applications.
• Implement neuromorphic-inspired on-chip signal processing within the ASIC to enable real-time classification of biosignals. This will involve hardware architectures for event-driven computation, low-latency pattern recognition, and adaptive feature extraction, specifically tailored to the statistical and temporal properties of the targeted biosignals. The neuromorphic processing block will be co-optimized with the AFE to ensure high classification accuracy while maintaining ultra-low power operation.
• Conduct pre-layout simulations, physical design, verification, and tapeout of the ASIC, followed by fabrication optimized for integration density, low power consumption, and low-noise operation.
• Perform post-silicon validation using neuromorphic biosensor arrays in a physiological monitoring setup to assess functionality, noise performance, and signal integrity under representative operating conditions.
• Develop a miniaturized system-on-chip (SoC), followed by post-packaging evaluation to characterize sensing performance, power efficiency, and wireless communication reliability.
• Integrate the final SoC into an implantable prototype and conduct validation in controlled health-monitoring scenarios.

The PhD student leading the ASIC development will work at both CMST, UGent and imec Leuven and is expected to drive and understand the full readout chain, especially through the first working prototype and to efficiently collaborate with the NEFELI team for sensor data and testing.

Skills and background:

• Solid knowledge of analog and mixed-signal integrated circuit design with foundation knowledge of signal-processing theory and hardware algorithms.
• Experience with IC design and simulation tools (Cadence Virtuoso, Spectre, etc.).
• Knowledge of digital circuit design is a plus.
• Experience with bench evaluation and PCB design; FPGA/embedded firmware experience is a plus.