/Physically Interpretable Power, Capacitance, and Power-Density Modeling for Future GPU Architectures

Physically Interpretable Power, Capacitance, and Power-Density Modeling for Future GPU Architectures

Master internship, PhD internship - Leuven | Just now

Technology-Aware GPU Power Models for Future Process Nodes
Modern GPU power models can accurately predict total power consumption, but they often provide limited insight into the underlying physical mechanisms responsible for power dissipation. This internship aims to bridge the gap between performance-counter-based power estimation and physically meaningful architecture characterization. The student will investigate how workload activity, voltage-frequency operating points, and architectural resources contribute to power consumption, and will develop methodologies to separate activity factors from technology-dependent parameters such as effective capacitance. The work will include feature analysis, DVFS-aware modeling, validation using architectural or RTL-level information, and the development of block-level power and power-density models. The ultimate goal is to establish a framework that not only predicts power accurately, but also supports technology-scaling studies, thermal analysis, power-density estimation, and future architecture exploration.


Type of internship: Master internship, PhD internship

Duration: 4-6 months

Required educational background: Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact Katayoon Basharkhah (Katayoon.Basharkhah@imec.be)

The reference code for this position is 2026-INT-303. Mention this reference code in your application.

Imec allowance will be provided for students studying at a non-Belgian university.


Applications should include the following information:

  • resume
  • motivation
  • current study

Incomplete applications will not be considered.
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