/Postdoctoral Fellowship - Design Engineer for 3D Architectures

Postdoctoral Fellowship - Design Engineer for 3D Architectures

Research & development - Indiana - West Lafayette | More than two weeks ago

Design Engineer for 3D Architectures  imec USA/Purdue University Joint Postdoctoral Fellowship

What You Will Do

Combinatorial optimization problems (COPs) are a subset of optimization problems aiming to find an optimal solution from a finite set of possible solutions. A common example is the travelling salesman problem with an objective to find the shortest route among candidate locations, visiting them only once. Efficienobjective functions to solve such problems, find use in diverse applications like network designtraffic management and logistics planning. Solving CoPs entails a large design space exploration (DSE) with multiple optimization targets and dynamic factors that need to be considered. Highly parallel computations can help exploring diverse solutions under different constraints. Ising machines proposed as domain specific accelerators (DSAs), have been used to solve TSP with minimal energy and execution time. However it is still challenging to scale-out to a larger design space with highly parallel compute elements with the necessary memory bandwidth. 

3D bonding technologies have shown great promise in terms of form factor reduction, high memory bandwidth and interconnect optimization. 3D design also comes with limitations in terms of thermal and IR drop, especially for advanced logic technologies. This research topic will focus on a DSE for highly parallel computation of large scale CoPs with workload complexities and the role of fine-pitch 3D connectivity for minimal energy solutions. 

To fortify 3D system technology co-optimization (STCO) research on ising machines for CoPsimec is seeking highly skilled electrical/electronic engineering Postdoctoral Fellow to advance these activities in the United States. This role involves collaboration between imec and Purdue University and will be co-advised by an imec technical manager and a Purdue faculty member. The position will be stationed at our new imec USA site located on Purdue University’s campus in West Lafayette, Indiana.

As the Successful Candidate:

You will analyze large scale CoPs and recent state-of-the-art literature and formulate a design space exploration for massively parallel ising machines. As a next step, you will analyze how can sub-micron pitch 3D bonding technology help to compute large-scale TSP faster with minimal energy. This 3D technology enabled DSE study will be further extended to assess the impact of emerging memory technologies for an improved system efficiency pareto front. Your work will take place in Purdue University's facilities as well as in imec research labs, collaborating with an international, multidisciplinary team. Regular participation and contributions to project and team meetings is expected.

Who You Are

  • Recently completed (or soon to complete) a Ph.D. in Electrical/electronic  Engineeringor computer science .

  • Experience with machine learning and optimization algorithms.

  • Knowledge and appreciation of emerging logic, memory and 3D technologies.

  • Hands-on experience with ML or DSA design space exploration tools is an advantage.

  • Published in top-level conferences and/or high-impact journals in the field.

  • Self-motivated, independent, innovative, results-driven yet rigorous, and a team player with a clear focus on delivery.

  • Strong communication, interpersonal, and organizational skills to bridge research groups and project partners in an interdisciplinary team.

  • Excellent verbal and written communication skills, fostering seamless interaction with local and remote colleagues and partners.

  • Adaptable to an international collaboration and willingness for regular visits to imec headquarters in Belgium.

This opportunity invites you to be part of pioneering research and innovation within an international, diverse and dynamic environment.

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