Power modeling of high bandwidth memories for AI applications

This internship will focus on extending an existing SRAM/eDRAM memory compiler to generate not only functional memory instances but also power  and simulation friendly abstracted views suitable for high bandwidth power integrity and thermal analysis. In advanced CMOS 2.0 contexts, accurately capturing dynamic power delivery, local IR drop behavior, and thermal hotspots becomes essential, especially as workloads stress memory arrays with rapid burst activity. To enable this, the work will develop a simplified yet physically meaningful modeling framework that represents the SRAM’s internal hierarchy - bitcells, wordline/bitline drivers, decoders, sense amplifiers - and their interaction with a coarse grained power distribution network (PDN). The internship will derive compact dynamic power signatures, activity dependent current waveforms, and parametrized PDN blocks that can be integrated into system level simulators for fast what if exploration of memory dominated bandwidth scenarios. The resulting flow will allow architects to evaluate power delivery robustness and thermal limits early in the design phase, bridging the gap between detailed implementation and system level analysis.
 

Type of Internship: Combination of internship and thesis; Internship; Master internship

Master's degree: Master of Engineering Science

Duration: > 6 months

Required educational background: Electrotechnics/Electrical Engineering

For more information or application, please contact the supervising scientists Fernando Garcia Redondo (fernando.garciaredondo@imec-int.com), Pieter Weckx (pieter.weckx@imec.be), Matthew Walker (matthew.walker@imec-int.com) and Geert Van der Plas (geert.vanderplas@imec.be).