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RC Delay Simulation of Advanced-Patterned Nano-Interconnects
Master internship - Leuven | Just now
Explore how advanced nanoscale interconnect patterns affect resistance-capacitance delay in future semiconductor technologies.
As semiconductor technologies continue to scale, interconnect performance has become a key factor limiting overall circuit speed, power efficiency, and technology scaling. In advanced back-end-of-line (BEOL) interconnects, resistance-capacitance (RC) delay is strongly influenced by conductor dimensions, dielectric spacing, material properties, and local layout geometry. With the introduction of advanced patterning approaches, future nano-interconnects may no longer be limited to simple straight and regular line structures, but may include more complex geometries such as non-uniform spacing, local width variation, curved segments, irregular patterns, and other layout-dependent features.
The goal of this internship is to simulate RC delay in advanced-patterned nano-interconnects. The project will study how nanoscale geometrical variations affect resistance, capacitance, and signal delay. Special attention will be given to the electrical impact of local pattern features, such as line width variation, spacing variation, curvature, line-edge effects, and local layout density. By comparing different interconnect pattern configurations, the project aims to identify the key geometrical and physical parameters that control RC delay in advanced BEOL structures.
The student will work on building, modifying, or applying a simulation workflow for extracting electrical parameters from representative nano-interconnect layouts. This may include geometry generation, resistance and capacitance estimation, numerical simulation, parameterized studies, and data analysis. Depending on the progress of the project and the background of the student, the work may also include simplified compact modeling or comparison with reference straight-line interconnect structures.
During the internship, the student is expected to:
- Become familiar with BEOL interconnect scaling challenges and RC delay concepts.
- Understand how interconnect geometry, spacing, and material properties influence electrical performance.
- Build, modify, or apply simulation workflows for advanced-patterned nano-interconnect structures.
- Extract and analyze resistance, capacitance, and RC delay from different pattern configurations.
- Compare advanced-patterned layouts with conventional straight interconnect geometries.
- Identify the key layout and physical parameters that dominate RC delay.
- Document the simulation methodology, analysis results, and main physical conclusions.
This internship is suitable for a motivated Master student interested in semiconductor interconnect technology, electrical modeling, numerical simulation, and advanced IC design. The outcome of the project will contribute to a better understanding of how advanced nanoscale interconnect patterns affect circuit-level performance and may support future technology exploration for advanced BEOL integration.
Type of internship: Master internship
Duration: 7 months
Required educational background: Electrotechnics/Electrical Engineering, Materials Engineering, Nanoscience & Nanotechnology, Other
Supervising scientist(s): For further information or for application, please contact Yu Fang (Yu.Fang@imec.be)
The reference code for this position is 2026-INT-196. Mention this reference code in your application.
Imec allowance will be provided for students studying at a non-Belgian university.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.