Research & development - Leuven | Just now
The continued scaling of CMOS logic and memory technologies is increasingly limited by the performance, resistivity, and integration complexity of advanced metallization schemes. As device architectures transition to deeply scaled nodes and 3D structures (e.g., CFET, high-aspect-ratio interconnects, and advanced memory stacking), conventional materials and processes such as Cu dual damascene face fundamental challenges related to line resistance, electromigration, barrier thickness overhead, and integration thermal budgets. This drives the need for novel metal systems (e.g., W, Mo, Ru alternatives) and highly controlled thin film deposition techniques capable of delivering conformal, uniform, and interface-engineered layers in complex geometries. Advanced deposition processes—such as ALD, CVD, and PVD—must enable precise control over material properties and interfaces while remaining compatible with increasingly stringent dimensional, thermal, and reliability constraints, making R&D in metallization a key enabler for sustaining performance scaling in future logic and memory technologies.
You will be a member of the Thin Films Advance Materials and Processes (TFAMP) group within the Materials, Interfaces, Deposition and Analysis (MIDA) department, responsible for developing, optimizing, and integrating next‑generation thin film processes to enable scaling in logic and memory devices, with a focus on metal systems such as Cu, W, and emerging alternatives like Mo. The role involves designing and executing experiments to develop highly conformal and low‑resistivity films using techniques such as ALD, CVD, and PVD, ensuring precise control of interfaces, gapfill performance, uniformity, and reliability in complex 3D architectures required for advanced nodes. The engineer analyzes interactions between material chemistry, process conditions, and equipment to improve electrical performance (e.g., resistivity, barrier integrity) and manufacturability, while collaborating closely with integration, device, and equipment teams as well as external suppliers. Responsibilities also include thin film characterization, root-cause analysis of process issues, and driving innovation in metallization schemes to meet future technology roadmap requirements, including low thermal budgets and compatibility with advanced interconnect and memory structures. By actively contributing to imec’s different program activities you will be part of the future semiconductor technology.
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee-based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.