Reconfigurable SRAM port size using hybrid SRAM

This MSc project will explore the design, modelling, and characterization of multiport SRAM arrays that exploit IGZO devices as BEOL integrated passgates to achieve significant area savings and enhanced scalability for AI centric high bandwidth access patterns. Traditional multiport SRAMs suffer from substantial area overhead due to the duplication of read/write access transistors; integrating ultra low leakage IGZO passgates above the silicon layer offers a path to decouple port scalability from FEOL constraints, enabling more ports without proportional area growth. The research will investigate co optimization between IGZO device behaviour and multiport SRAM circuit topology, including timing critical interactions between passgate characteristics, bitline/wordline loading, contention scenarios, and retention under concurrent operations. The project will further examine write driver and sense amplifier adaptations tailored to IGZO based pass elements, performing sensitivity analyses to quantify the impact of IGZO threshold shifts, gate leakage, parasitic coupling, and temperature dependent behaviour on multiport robustness. The final outcome aims to define design guidelines and architectural trade offs for deploying IGZO enabled multiport SRAM in next generation low latency, high throughput AI accelerators.
 

Master's degree: Master of Engineering Science; Master of Science

Required educational background:  Electrotechnics/Electrical Engineering

Duration: >5 months

For more information or application, please contact the supervising scientists Fernando Garcia Redondo (fernando.garciaredondo@imec-int.com), Pieter Weckx (Pieter.Weckx@imec.be) and Ankit Singh (Ankit.Singh@imec.be).