[NanoIC topic] Research on High Aspect Ratio Dielectric Etch for 3D Integration

Chip downscaling is pushing the boundaries of what can be achieved with conventional plasma etch tools, especially for HAR dielectric etch, necessary for several technologies, as MOL interconnect scaling and memory applications (3DNAND, 3DDRAM). The use of cryogenic etch processes may enable future nodes of these technologies by achieving higher AR patterning. The use of cryogenic temperatures during the dielectric etch processes enables different chemical reactions happening at the interface of the dielectric layers (silicon oxide, silicon nitride, among others) so that faster etch rate, straighter profiles and more environmentally friendly etch processes than covnentional etch (at high temperature, above room temperature) can be obtained.

This PhD offers the opportunity to work with state-of-the-art cryogenic and high temperature plasma etch tools and work in close collaboration with the tool suppliers to get a broader understanding of the current technology limitations and to gain deeper understanding of the fundamentals to propose novel approaches that enables future technology nodes.

The candidate will be fully trained for cleanroom access and operation of plasma etch and metrology tools. Design of Experiments (DoE) and other relevant trainings will be provided so the candidate will have the necessary tools to tackle the research topic. The workload is expected to be mostly experimental and data analysis (~80%) with strong need to work inside the cleanroom environment to perform experiments. This project expects high cientific output in the shape of international conference and published manuscripts, given the broad application of cryogenic etch processes and the not so much information that is publicly available in the literature.