Row hammer effect for IGZO based eDRAM using TCAD

The project will investigate TCAD based implementation and analysis of 2T0C and 3T0C IGZO memory arrays to understand their susceptibility to row hammer like disturbance mechanisms. Unlike silicon gain cell structures, IGZO devices exhibit ultra low leakage and strong bias temperature dependence, requiring physics based TCAD models to accurately capture charge retention, gate leakage driven decay, and array level coupling effects. By constructing array scale TCAD environments incorporating realistic wordline/bitline parasitics, device variability, and thermal conditions, the internship will evaluate how repeated activation of neighboring rows affects storage node stability, sensing margins, and long term reliability in IGZO eDRAM architectures. This work aims to provide predictive insights into disturbance induced failure modes and to guide robust circuit level mitigation strategies.
 

Type of Internship: Internship; Thesis; Combination of internship and thesis; Master internship

Master's degree: Master of Science; Master of Engineering Technology

Required educational background: Electrotechnics/Electrical Engineering

Duration: >5 months

For more information or application, please contact the supervising scientists Arvind Sharma (arvind.sharma@imec.be), Aishwarya Singh (aishwarya.singh@imec.be), Subhali Subhechha (subhali.subhechha@imec.be) and Shankha Mukherjee (shankha.mukherjee@imec.be).