In-situ monitoring for workload-dependent variability in AI digital circuits

Artificial Intelligence (AI) systems rely on advanced semiconductor technologies that are increasingly affected by device variability and aging effects, such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Electromigration (EM). These phenomena can gradually degrade circuit performance and eventually lead to timing failures and silent data corruption. Root causes include logic-path failures, along with register file and SRAM memory errors. While in-situ monitors, error-recovery flip-flops, and memory protection schemes can mitigate these effects, their overhead limits widespread deployment.

This PhD aims to develop innovative in-situ monitoring and recovery techniques that detect and mitigate degradation-induced failures. Furthermore, by leveraging the workload dependence of physical aging mechanisms, the project seeks to optimize the deployment of such monitoring and recovery circuitry, improving reliability while minimizing cost in area, power, and performance.

The research will combine circuit design, reliability modeling, and electronic design  utomation (EDA) to create a workload-aware methodology that predicts aging effects and optimizes the placement of monitoring circuitry. The proposed solutions will be validated through implementation in an advanced semiconductor technology node, including silicon measurements and evaluation of future technology generations using imec's predictive process design kits. The project offers a unique opportunity to contribute to the reliability, energy efficiency, and long-term robustness of next-generation AI hardware platforms.