Solid-State Ionic Gating of Emerging Low-Dimensional Semiconductors for CMOS Applications

Recent work has demonstrated that solid electrolytes can provide strong electrostatic coupling through electrical-double-layer formation, enabling low-voltage transistor operation and novel device functionalities. Electrolyte-gated devices have been explored for oxide electronics, neuromorphic computing, and ionic-electronic hybrid systems, including lithium-ion synaptic transistors and all-solid-state electrolyte-gated transistors. These studies show the potential of solid-state ionic gating to achieve high carrier densities and device functions that are difficult to obtain with conventional dielectric gate stacks.

While solid-state electrolyte-gated transistors have shown promising electrostatic control and new device functionalities, their suitability for mainstream logic remains unproven. Existing work has focused mainly on oxide electronics and neuromorphic devices, with limited investigation of low-dimensional semiconductor channels such as CNTs and 2D materials. Key challenges remain unresolved: whether ionic gating can support switching at CMOS-relevant speeds, whether solid electrolytes can be integrated in CMOS-compatible process flows, and whether devices can satisfy reliability and operating-temperature requirements for logic technologies. It is also not yet clear whether solid electrolytes can provide high-capacitance gate coupling without introducing the interface defects and performance degradation often associated with conventional dielectric deposition on low-dimensional semiconductors.