Standard cells Design Exploration using advanced Nodes

To support our ever-growing need for higher functionality per area, CMOS technology has evolved rapidly. However, each step towards newer technology has also been accompanied by newer challenges from perspective of manufacturing, design, and implementation. It is the resolution of these challenges via exploration and systematic trial that drives this evolution. In recent times, one such critical challenge in the design space has been crowding in routing resource in conjunction with area intensive power delivery network (PDN). Moving in the direction to resolve this challenge a new alternative of using backside PDN (BPDN) has gained traction. 
The standard cell design has always been sensitive to smallest of technological change considering different operating condition scenarios. Thus, there has always been a need for new designs and implementation methodologies for newer technologies. This project involves using BPDN for designing new standard cells and studying the performance compared to standard front side power technology and finding alternatives to meet target specifications. 
 
Requirements to fulfil this project:

• Understanding of CMOS technology
• Strong knowledge in spice simulations. 
• Knowledge of Linux 
• Strong programming skills in Python, Perl, shell
• Communicative and active team player

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Science; Master of Science 

Master program: Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology 

Duration: 3 - 4 months 

Supervising scientist: For more information or application, please contact Arka Dutta (arka.dutta@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.