/Stress Modeling in CFET

Stress Modeling in CFET

Master projects/internships - Leuven | More than two weeks ago

CFETs, or complementary field effect transistors, may be a key enabler for future transistor technology nodes. These devices have n- and p-MOS functionality layered on top of each other in a gate-all-around configuration. They are therefore highly complex, both in built and function, and require extensive study to comprehend possible design, material, and process interactions.

In this internship, you will study strain in CFET devices as a key modulator of transistor performance. You will explore the effect of process and material selection on device structures fabricated in the imec 300mm line to help guide future R&D efforts.

You will work in close collaboration with experts from leading industry partners and the imec TCAD and CFET integration teams.


Type of project: Internship

Required degree: Master of Engineering Science

Required background: Electrotechnics, Electrical Engineering

Duration: at least 3 months

Supervising scientist(s): For more information on this topic, please contact Philippe Matagne (Philippe.Matagne@imec.be) and Nicole Thomas (nicole.thomas.ext@imec.be).

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