Technology-driven logic synthesis for emerging transistor technologies

Logic synthesis turns a design into gates with cost models that were written for the technologies of the past: a cell costs what its library entry says, and the structure of the circuit below the gate is invisible to the tool. Emerging transistor architectures change what is cheap and what is expensive at the circuit level, and emerging workloads change which logic structures matter. A synthesis flow that cannot see either leaves most of the technology's potential on the table.

The student will work on synthesis flows that bring technology awareness into the loop: physically grounded cost models for logic at the transistor and cell level, their use inside technology mapping and optimisation with open synthesis tools, and an evaluation on benchmark designs that shows how much a technology-aware flow gains over a conventional one and where the gains come from.