PhD - Leuven | Just now
Strain engineering has become an essential technique for continued transistor performance scaling beyond the traditional limits of dimensional scaling [1-2]. By modifying the semiconductor crystal lattice, strain enhances carrier mobility and drive current without increasing power consumption. While strain engineering concepts have been successfully implemented in semiconductor manufacturing for more than two decades, maintaining precise strain control in emerging gate-all-around (GAA) nanosheet (NS) and complementary field effect transistor (CFET) architectures remains a critical challenge because of their complex three-dimensional (3D) geometries, scaling, reduced dimensions, and increasing material diversity.
This PhD research hypothesizes that the observed strain non-uniformity in stacked nanosheet transistors originates from process-induced strain contributions that evolve throughout device integration. The project seeks to answer several key research questions: How does strain evolve from Si/SiGe epitaxy to the final GAA device? What mechanisms drive nanosheet-to-nanosheet strain variability within a single device? Can nanoscale strain be quantitatively linked to device-level performance? To what extent can local electronic, and dielectric properties be correlated with strain and compositional variations? Finally, what causes the systematic discrepancies often observed between Technology computer-aided design (TCAD) predictions and experimentally measured strain distributions?
The overarching scientific objective of this PhD is to establish an understanding of the origin, evolution and consequences of strain variability in advanced GAA NS and CFET devices. While strain engineering is a key performance, the mechanisms governing strain evolution in 3D stacked transistor remains insufficiently understood. Existing studies provide accurate strain measurements, but the causal relationships between process integration, local strain distribution, material properties and device behaviour are still largely unexplored.
The research will combine advanced transmission electron microscopy (TEM) techniques with state-of-the-art electron energy-loss spectroscopy (EELS). Quantitative strain characterization will be performed using 4D-STEM approaches supported by TCAD simulations. Complementary Raman spectroscopy may be used as a non-destructive strain metrology technique, providing independent measurements of strain-induced phonon shifts and enabling correlation between future strain wafer-scale device characterization and local TEM-based strain mapping.[3] Monochromated low-loss EELS will be employed to probe local bandgap variations, dielectric response, plasmonic excitations and, where experimentally feasible, vibrational properties in NS and CFET devices [4-5]. In parallel, core-loss EELS and complementary compositional analysis techniques such as atom probe tomography (APT) will be used to investigate the interplay between strain, chemical composition, and dopant distributions [6-7]. Experimental observations will be compared with physic-based simulations, including TCAD and potentially density functional theory (DFT) based EELS modelling, to separate strain induced effects from compositional and doping related contributions.
The project aims to establish quantitative relationships between local strain, dielectric properties, electronic structure, phonon response and ultimately carrier mobility. By bridging the gap between atomic scale characterization and device-level optimization, the research will provide new insights for process development and stress engineering strategies in future semiconductor technology nodes, directly supporting the development of next generation logic devices.
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Required background: Physics, Material science or equivalent
Type of work: 50% experimental, 30% simulation, 20% theory
Supervisor: Claudia Fleischmann (KU Leuven)
Co-supervisor: Claudia Fleischmann (KU Leuven)
Daily advisor: Paola Favia
The reference code for this position is 2027-053. Mention this reference code in your application.